How to reduce the influence of the PAD to the circuit

Hi,
I am disign a LNA circuit, the parameters of it is good enough for my goal when pre-simulation and post-simulation without PAD.
But when I add the PADS to the circuit layout, the post-simulation results become bad, the |S11| decreased 1.5 dB and |S22| decreased 8dB when in High frequency, it made my circuit work badly.
Is there any PAD structure can fit the RF usage, please?

Thank you!
Best regards!

If is a CMOS LNA you can try to add a capacitor on each pin of the LNA, capacitor having the same value with the parasitic capacitance of the PAD, and tune again the entire circuit.

Thank you for your reply.
What trouble me is the parasitic capacitance of the PAD, as the PAD is at least 70um*70um large, they will introduce a large capacitance in the input and output point.
I try to add a capacitance in the circuit in pre-simulation, but I do not know what value should the capacitance be, Because the PAD is make up by M4-M3-M2. Some one told the parasitic capacitance of the PAD is about 1pF in 70um*70um area, but when I add a 1pF capacitance to the circuit input, the circuit could not work any more, but I use the RCX netlist for post-simulation, the result will not be so bad, so I think the parasitic capacitance will not be so large, what value should it be, please?

And can I caculate the capacitance of one point from the RCX netlist by but the tools of hspice or spectre?

And is there any PAD structure without so large parasitic capacitance and can fit the RF use, please?

Thank you!
Best regards!

I cannot predict your PAD capacitance. You have to simulate it.
The parasitic capacitance of the PAD is given by the surface of the PAD and by the thikness and Er of the substarte.
In general diamond-shaped PADs are used to reduce the parasitic capacitance.

If you have a square pad you can cut the corners and have an octagonal pad. I do not think your pad can have 1pF capacitance but rather 250fF (of course, it depends on your technology).

Hi, I have faced the same problem some time ago. First of all. You should be able to extract the parasitic C of the pad from the layout. Otherwise you can also calculate it from the foundry documentation. You have touse the lower metal to substrate capacitance per unit area.

In any case what you should do is to create your own pad with only top metal. Remove the lower metals to reduce the parasitic cap (the larger the distance to the substrate, the smaller the parasitics). Pay attention to the ESD circuit so you don't spoil it!

BTW. My estimation for the pad is halfway both ;-) My guess is 500fF

Just one consideration on what PaloAlto said: if you use the top metal only, check your pad rules. Sometimes you have to have more layer for bond-ability and mechanical resistance. If your top metal is not "strong" enough, you might have problems bonding your chip.

yep, you need to make sure that your new pad can stand the stress