brunokasimin
Member level 4
Hello,
I assign both outputs and inputs of my uart vhdl codes to the 9 pins of rs232.Is that correct?? In the entity part of the uart vhdl code below, rx_data_out and tx_data_in are 8 bits width.I don't know how to assign them with the pin of rs232..anyone can help me??
entity uart_serial is
port(
-- Global signal
areset : in std_logic; -- reset control signal
clk : in std_logic; -- 14.7456 Mhz Clock frequency
-- Reception channel
rx_data_serial : in std_logic; -- Received Serial data from RS232
rx_data_out : out std_logic_vector(7 downto 0); -- Received Data
rx_data_en : out std_logic; -- Received data enable control signal
rx_ovf_err : out std_logic; -- Received data over frame error detected
rx_parity_err : out std_logic; -- Received data parity error
-- Transmition channel
tx_data_serial : out std_logic; -- Transmited Serial data to RS232
tx_data_in : in std_logic_vector(7 downto 0); -- Transmited data
tx_data_en : in std_logic; -- Transmited data latch enable
tx_ch_rdy : out std_logic; -- Transmition channel ready status signal
-- Control command
baud_sel : in std_logic_vector(3 downto 0); -- Baud value see Note
parity_en : in std_logic; -- Enable parity control signal active HIGH
parity_type : in std_logic); -- 1:ODD parity / 0:EVEN parity
end entity;
thx
I assign both outputs and inputs of my uart vhdl codes to the 9 pins of rs232.Is that correct?? In the entity part of the uart vhdl code below, rx_data_out and tx_data_in are 8 bits width.I don't know how to assign them with the pin of rs232..anyone can help me??
entity uart_serial is
port(
-- Global signal
areset : in std_logic; -- reset control signal
clk : in std_logic; -- 14.7456 Mhz Clock frequency
-- Reception channel
rx_data_serial : in std_logic; -- Received Serial data from RS232
rx_data_out : out std_logic_vector(7 downto 0); -- Received Data
rx_data_en : out std_logic; -- Received data enable control signal
rx_ovf_err : out std_logic; -- Received data over frame error detected
rx_parity_err : out std_logic; -- Received data parity error
-- Transmition channel
tx_data_serial : out std_logic; -- Transmited Serial data to RS232
tx_data_in : in std_logic_vector(7 downto 0); -- Transmited data
tx_data_en : in std_logic; -- Transmited data latch enable
tx_ch_rdy : out std_logic; -- Transmition channel ready status signal
-- Control command
baud_sel : in std_logic_vector(3 downto 0); -- Baud value see Note
parity_en : in std_logic; -- Enable parity control signal active HIGH
parity_type : in std_logic); -- 1:ODD parity / 0:EVEN parity
end entity;
thx