Use Metal layer drawing put text on layer

pin label

Hi everybody

When I generate layout by use SOC I see that text put on layer is same that layer.
Example text I111 put on MTL1(drawing) is layer MTL1(drawing)

I know when tape out is text I111 is MTL1 and I worry it will make short with different MTL1(regtangular). Is it true?

Please help me, thanks

spnet map

Hello,

Each technology/foundries have different naming conventions and procedures. I am just providing one of the methods.

Usually when pins are created they are created by using Metal pin layer for drawing pinshape(rectangle/polygon) and Metal text layer for labeling the pinname.

Ex: A pin on Metal1 is created as follows:
On Metal1(drawing) ---> Metal1(pin) ---> Metal1(text)

By following this procedure you will not short with any Metal1's, but make sure that you do not overlap this pinlayer with any other same metal pinlayers.

For Labels you can use just the Text layer.

Hope this helps you.

Paramjyothi

Thanks Paramjyothi,

I knew about Text Layer,

but I put Label on Metal1 (drawing) by using Metal1 (drawing) and my project
had taped out

I want to know whether will Label(Metal1(dg)) process by fab? And if yes, do it make
short different MTL1(dg).

Please help me!

Hello,

Label is only for our identification purposes and shall not short with anything, but since you have used Metal1(dg) for label on Metal1 itself it will not be a problem.

But Shorting of the label with other Metal1's is possible only if your Label has a very big font and overlaps with other M1's passing side by. Actually an error should have been flagged when you ran DRC/LVS? Didn't you get an error during your LVS runs?

Hope your Label font is small and no other M1 nets are passing side by.

Paramjyothi

Can you specify if you are talking about labels (like wire labelled VIN) or if you have drawn shapes to make letters?

What you really want to do is call the fab and ask for the jobview for your project. Then you can see what is actually on the mask - and anything on the mask will be in the final chip. So if you have metal text crossing metal lines they will all be connected.

Thanks for everybody's reply,

I run DRC and LVS but no error, label is big font and I'm talking about label(like wire labelled VIN) not shape to make letter.

I will see my project jobview,

Thank you very much,

If it's just a label it will should not show up in your GDS data. But it's best to verify that using jobview because I am not clear enough on your tool and situation to guarantee it for you.

btw what tool you using for your layout

I SOC to generate layout and file streamout.map of TSMC is:

METAL1 ALL 16 0
NAME METAL1/NET 16 0
NAME METAL1/SPNET 40 0
NAME METAL1/PIN 40 0
NAME METAL1/LEFPIN 16 0
VIA12 ALL 17 0
METAL2 ALL 18 0
NAME METAL2/NET 18 0
NAME METAL2/SPNET 41 0
NAME METAL2/PIN 41 0
NAME METAL2/LEFPIN 18 0
VIA23 ALL 27 0
METAL3 ALL 28 0
NAME METAL3/NET 28 0
NAME METAL3/SPNET 42 0
NAME METAL3/PIN 42 0
NAME METAL3/LEFPIN 28 0
VIA34 ALL 29 0
METAL4 ALL 31 0
NAME METAL4/NET 31 0
NAME METAL4/SPNET 43 0
NAME METAL4/PIN 43 0
NAME METAL4/LEFPIN 31 0
VIA45 ALL 32 0
METAL5 ALL 33 0
NAME METAL5/NET 33 0
NAME METAL5/SPNET 44 0
NAME METAL5/PIN 44 0
NAME METAL5/LEFPIN 33 0
NAME COMP 62 0
#COMP ALL 89 0
#DIEAREA ALL 90 0

Because METAL1/NET 16 0, so name net MTL1 same MTL1 (dg), and GDS have name net MTL1, and it make me worry!

All text features are removed during masks preparation in the fab. no worry about these labels made by Metal layer, this is the reason you didnt get any LVS errors and sure no DRC with your layout.

Regards,

Thanks for your reply very much,