Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

logic to detect 1 bit (only 1 bit) High in a bus

Status
Not open for further replies.

weng

Member level 1
Joined
Jan 13, 2006
Messages
32
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,576
I need to have a logic to detect ONLY 1 bit high in a bus.

For example:
a bus signal Y[3:0]. output OUT High only if Y == 0001 or Y == 0010 or Y == 0100 or Y == 1000.

What is the best way to code it in Verilog? In terms of min gate transition?
 

time as well as area optimize circuit will be a combinational circuit as follows
consider your bus is n bit in width then u need 'n' no of n-input NAND gate and one n-input OR gate and n no of NOT gates.
logic is simple , each NAND will detect a sequence containning one logic one . like wise there will be n sequence having singe one on it and therefore n nos of NAND gates. out put of all NAND will be given to OR.
 

depending how wide your bus is, but I would try to use FA (full adders).
this is not true addition logic since once you have a carry in one of the FA you can immediately bypass the result to the output, since it means you got more than 1 "1".
In some cases this would be faster and for sure less area (and power) than the fully paralleled approach.

ND.
https://asicdigitaldesign.wordpress.com
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top