Thread: cmos Voltage Step down/Step up detecting circuit in IC

can somebody explain how a cmos voltage step-up/step-down detecting device works? thanks a alot = )

I have never heard this term" step-up/down detecting".

Are you sure you don't mean step-up/down converter?

You can link to an example, then we will explain.

I was actually reading some patents and i found this one: http://www.google.com/patents?id=smY...ng+accelerator

I was looking at the invention's first embodiment. Please see figure 3 and 4(a and b).
Actually, its not only the detecting circuit that I was confused about but the whole cmos circuit itself. I dont understand how it was able to attain the waveforms in fig 4b. It was explained in the "summary of the invention" number 25 page 13, but I still dont get it why or how, basing on the circuit. Can you help me? thanks = )[/img]

Originally Posted by andrew_matiga

can somebody explain how a cmos voltage step-up/step-down detecting device works? thanks a alot = )

easy, use a fast responsed comparator and a delayed (slow responsed) 0dB buffer.

When voltage step-up, comparator will ouput '1', or else '0', then latch the data quickly.

you can use bulk structure for voltage down and booster for voltage up