chess clock vhdl code

vhdl clock code

Hi everyone
I m new comer coding in vhdl
I want to design fisher chess clock
So I need Vhdl code for fisher chess clock
Pls let me favour.
Bcoz I have to complete this project in Short
time.
thankshazwan

common cathode

student?

chess timer clock circuit

yes, i'am student. could you help me?

code vhdl clock

I tend not to do the homework of students.
However, everyone needs to learn...

So, let's analyse the system:
1. I don't know what a Fisher chess clock is, but I guess that it will be a variant of a seconds/minutes timer with start/stop/reset buttons.
What are your inputs/what outputs do you foresee?
Input:
Clk (usually something in the range of 10...50MHz)
Reset (hardware reset, not clock reset)
Pushbuttons for start, stop, game reset (maybe stop of first player can be start of 2nd player)
other inputs (for the moment, I don't see any)

Outputs:
some kind of display (LED, LCD, Video; asume LEDs): easiest form 4 7-segment LED displays

2. because you have pushbuttons, there will be need for a debounce system. The high clock frequency need to be divided to a 'one second' clk tick. The hart of the system is the clock counter itself. Then you need some sort of module that converts the decimal value to 7-segment information (common cathode or common anode). You can additionally choose to multiplex the 7-seg displays (usually done in FPGA to use less I/Os.

3. analyse further down:
a. debounce circuit (can be found on google). Think about it: the key can toggle in (maybe 100ms) a couple of times from one to zero and back. So you will need to develop a circuit that samples the values of the key input (sample frequency 50...200Hz - another output for your divider). If all the inputs of the samples are the same, then you are sure that the input is debounced. Up to you to convert this explanation in VHDL.

b. divider circuit. One of the basic circuits of a VHDL designer. Don't forget that every FF divides by two. Maybe you can simplify your clk input as a multiple of 2?

c. Hex->7-Seg: again a basic module that can easily found on the internet.

d. the toughest part is the seconds/minutes counter:
- start by thinking how you would do this manually
- second=0, 10-seconds=0, minutes=0, 10-minutes=0
- seconds = seconds +1
- if seconds = 10, 10-seconds = seconds+1; seconds = 0
- if 10-seconds=6, minutes=minutes+1, 10-seconds=0
- if minutes=10, 10-minutes= 10minutes+1, minutes=0
- now add the enable signals for start, stop, reset (shouldn't be that difficult)

Did I miss something?

Convert everything to VHDL of Verilog and your homework is done.

good luck