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Verilog Newbie - simple question

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davidgrm

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video test pattern in verilog

Hi

I am reading data out of a 32 bit rom and am trying to split it into 4 bytes. I am not getting the results that I expect and want to confirm that this snippet of code is correct:

case(ByteCount)
2'b00:
begin
ENC_DATA <= RomDataOut[31:24];
ByteCount <= 2'b01;
end
2'b01:
begin
ENC_DATA <= RomDataOut[23:16];
ByteCount <= 2'b10;
end
2'b10:
begin
ENC_DATA <= RomDataOut[15:8];
ByteCount <= 2'b11;
end
2'b11:
begin
ENC_DATA <= RomDataOut[7:0];
ByteCount <= 2'b00;
end
endcase
 

fthe use of for in verilog

Did you put these statements inside a clocked process or not?? "ByteCount" should be updated only after each clock cycle if i understood correctly.

if u havae already put this part of fthe code in clocked process, do post that part of the code as well.
 

Yep - I had it posedge, and then decided to try neg edge

always @(negedge ENC_CLOCK_2)
begin
case(ByteCount)
2'b00:
begin
ENC_DATA <= RomDataOut[31:24];
ByteCount <= 2'b01;
BlockDone <= 0;
end
2'b01:
begin
ENC_DATA <= RomDataOut[23:16];
ByteCount <= 2'b10;
end
2'b10:
begin
ENC_DATA <= RomDataOut[15:8];
ByteCount <= 2'b11;
end
2'b11: //all bytes done end of block reached
begin
ENC_DATA <= RomDataOut[7:0];
ByteCount <= 2'b00;
BlockDone <= 1;
end
endcase
end





PaterrnRom PaterrnRom_inst (
.address ( RomAddr ),
.clock ( ENC_CLOCK_2 ),
.q ( RomDataOut )
);
 

can you elaborate your problem so that it gets clear??

How about u r RomAddr, does it change often or would it be stable for atleast 4 clock cycles...because u have the same clock for splitting up tha data as well as collecting the data from the ROM
 

Well to start of I just want to confirm if the code presented will allow me to get 1 byte at a time from a 32 bit rom? Currently for testing I have set the address to 0. I used the negative edge because Quartus indicates that the rom will clock the data out on the positive edge, so I thought it might not be stable on that edge. The problem is I dont seem to get the data out that I put in :( This is just a snippet of code. I am trying to write a video test pattern to a video encoder chip. Unfortunatly the test pattern has a whole lot of 4 byte blocks that need to repeated various number of times. That is why I decided to create a 32 bit rom instead of an 8 bit rom. It is the basic rom that is available as a megafunction in Quartus. I am assuming that it can handle speeds of 27Mhz???
 

Basically, it's rather a question of RTL design than a Verilog specific matter, I think.
I used the negative edge because qu(at)rtus indicates that the rom will clock the data out on the positive edge
In this case posedge would be the usual solution. In a synchronous design, data are safely transfered between registers clocked at the same edge, this also applies to FPGA embedded memory.

Considering Cyclone II M4K blocks for example, they can be used as 128x32 or 512x8 memory as well. Using the byte wide memory wouldn't require a data multiplexer, just the multiplex clock at two address lines. There’s more than one way to skin a cat, however.
 

Are there any possible reasons why I should get incorrect data coming out of the Cyclone Rom? ie any settings required? I am using the Quartus memory editor to create a 32bit hex file
 

I wouldn't expect any, particularily without timing conflicts found in timing analysis.
 

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