davidgrm
Full Member level 4
video test pattern in verilog
Hi
I am reading data out of a 32 bit rom and am trying to split it into 4 bytes. I am not getting the results that I expect and want to confirm that this snippet of code is correct:
case(ByteCount)
2'b00:
begin
ENC_DATA <= RomDataOut[31:24];
ByteCount <= 2'b01;
end
2'b01:
begin
ENC_DATA <= RomDataOut[23:16];
ByteCount <= 2'b10;
end
2'b10:
begin
ENC_DATA <= RomDataOut[15:8];
ByteCount <= 2'b11;
end
2'b11:
begin
ENC_DATA <= RomDataOut[7:0];
ByteCount <= 2'b00;
end
endcase
Hi
I am reading data out of a 32 bit rom and am trying to split it into 4 bytes. I am not getting the results that I expect and want to confirm that this snippet of code is correct:
case(ByteCount)
2'b00:
begin
ENC_DATA <= RomDataOut[31:24];
ByteCount <= 2'b01;
end
2'b01:
begin
ENC_DATA <= RomDataOut[23:16];
ByteCount <= 2'b10;
end
2'b10:
begin
ENC_DATA <= RomDataOut[15:8];
ByteCount <= 2'b11;
end
2'b11:
begin
ENC_DATA <= RomDataOut[7:0];
ByteCount <= 2'b00;
end
endcase