integer size is 32 bit in Verilog. Can we extend it? In VHDL we can
have something like,

Max_Time : in integer range 0 to 255;

How do we express this in Verilog?

Thanks
Swapnil

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2. ## signed integer in verilog

First:
Your example of a VHDL integer in the following statement has only a 8 bit integer.
Max_Time : in integer range 0 to 255
I dont quite understand what to you mean 'extend'. Extend beyond 32 bits?
Then take a reg/wire type and have as many bits as you like in it. And in verilog you can use the reg type vectors just as you would integers.
Hope it helps
Kr,
Avi

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3. ## integer data type verilog

Integer has a partly different purpose i Verilog. IEEE spec says
An integer is a general-pupose variable used for manipulating quantities that are not regarded as hardware registers.
Thus integer has no range. A reg e. g. can't be of the integer type.

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Originally Posted by FvM
Integer has a partly different purpose i Verilog. IEEE spec says
An integer is a general-pupose variable used for manipulating quantities that are not regarded as hardware registers.
Thus integer has no range. A reg e. g. can't be of the integer type.
In Verilog-2001, a Verilog "integer" is a 32-bit signed value. So it has a finite minimum and maximum range. (A Verilog "real" is a floating-point value.)

If you need more than 32-bits, you can simply declare a signed reg/wire with as many bits as you want.

Code:
```reg  signed [31:0] int32;
reg  signed [63:0] int64;
reg  signed [127:0] int128;
wire signed [127:0] int128_wire = int128;```

5. ## verilog signed reg

Originally Posted by boardlanguage
Originally Posted by FvM
Integer has a partly different purpose i Verilog. IEEE spec says
An integer is a general-pupose variable used for manipulating quantities that are not regarded as hardware registers.
Thus integer has no range. A reg e. g. can't be of the integer type.
In Verilog-2001, a Verilog "integer" is a 32-bit signed value. So it has a finite minimum and maximum range. (A Verilog "real" is a floating-point value.)

If you need more than 32-bits, you can simply declare a signed reg/wire with as many bits as you want.

Code:
```reg  signed [31:0] int32;
reg  signed [63:0] int64;
reg  signed [127:0] int128;
wire signed [127:0] int128_wire = int128;```
This is representing integer in 32/64/128 bits. This is NOT integer datatype defined in verilog standard. I don''t have spec handy right now to quote, but I believe it makes it very clear that integer data type is simulator dependent when it comes to min-max range. Or put it like this, simulators are free to choose as many bits as they want to internally represent integer datatype. Integer datatype should not be used to represent hardware that you intend to synthesize and see in real silicon.

Here is the relavant section for verilog-2001 spec.

Look for this line :

NOTE Implementations may limit the maximum size of an integer variable, but they shall at least be 32 bits.

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