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Why no negative voltages in CMOS circuits?

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jgrant3

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Hello.

Can someone please explain to me why negative voltages are not commonly used with CMOS IC chips? Why is the technology always described as being 0-3.3 V or 0-5 V for example?

I ask because my colleague has found a topology which is for a 0.35 um process that works for -1.5 V to 1.5 V however for 0 -3.3 V the same topology does not work. Surely having negative voltages available makes life simpler?

Thanks
 

I think it's mostly a matter of compatability with digital processes. For digital design, there is no need for a -ve potential. Besides, it's more expensive to have dual supplies than to have a single supply plus ground.
 

elbadry said:
I think it's mostly a matter of compatability with digital processes. For digital design, there is no need for a -ve potential. Besides, it's more expensive to have dual supplies than to have a single supply plus ground.
Click to expand...

Thanks for your comments.

Dual power supplies are only slightly more expensive than single polarity ones so I do not think this is the reason. I was thinking that there must be a technoloyical reason why -ve voltages in CMOS IC design are rarely used however after numerous google searches I've yet to find the reason.

I take your point about -ve voltages not being required for digital design though.

Thanks again!
 

To me, having positive or negative voltages is a matter of convention.

Generally, in CMOS design, there is a supply, a ground, and possibly a common-mode reference provided (usually mid-supply). This could equally well be translated to a positive supply, a negative supply, and a 0-V ground.

If you give me a circuit that has 0 V and 3.0 V rails, I can make it work equally well off of -1.5 V & 1.5 V rails.

In portable applications (where there is no earth ground), there is nothing to reference absolute ground, so the circuit won't know the difference. In this case, the negative end of the battery is taken to be 0 V, and the positive to be VBAT. We could equally well call them -VBAT/2 and VBAT/2.

It is merely convention.
--
Poojan
https://www.circuitdesign.info
 

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    jgrant3

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All active devices in CMOS could not be operated below the substrate of the silicon. So the most negative supply is connected to this substrate and often called VSS.

For noise rejection reason in analog circuits there could be also a virtual ground, generated by clean circuits outside and buffered to internal and als referended.
 

Yes, rfsystem is correct. A typical NWELL process with p-type substrate requires the substrate to be connected to the lowest potential. Otherwise, you will turn on the P-N diode from substrate to your NWELL.

There are also N-substrate process (PWELL) that connects the substrate to the highest potential, but they are old and out of style.
 

I agree with electronrancher.
You can consider normal NMOS. The body diode will be forward-biased if its drain is negative.
 

electronrancher said:
Yes, rfsystem is correct. A typical NWELL process with p-type substrate requires the substrate to be connected to the lowest potential. Otherwise, you will turn on the P-N diode from substrate to your NWELL.

There are also N-substrate process (PWELL) that connects the substrate to the highest potential, but they are old and out of style.
Click to expand...

So it is possible to operate a CMOS chip that say has standard voltage ranges of 0-3.3 V (a la the AMS 0.35 um process), with an abnormal/unusual voltage range of -1.65V to +1. 65 V on the proviso that the p-type substrate is tied to the lowest postential (i.e. - 1.65 V)?

Many thanks to all!
 

Yes but be very very sure that the bulk connections of the NMOS (the p substrate or pwell) are then connected to their source or the lowest potential i.g. -1.65V. Most similators connect the bulks of NMOS to GND. If GND is not the lowest potential you need to hack your simulator.

And a CMOS chip should work as long a supply voltage is applied from gnd to vdd.
 

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