standup
Member level 1
The rectifier block uses a cascaded Dickson voltage multiplier circuit with multiple cascaded sections in order to convert the extremely low input voltage up to a potential suffi cient for operating CMOS circuits.
The bulk terminals of the PMOS transistors were tied to the gate and drain terminals (back-bias) to reduce the effective threshold voltage.
Could this configure work normally?
How to analyse the body-effect of PMOS?
Under this condition, the Source voltage is higher than the nwell voltage,the performance of PMOS must be affected.for PMOS,is the model fit to the condition Vbs<0?
thank you!
The paper will be uploaded later,the details are on the 7th page.
The bulk terminals of the PMOS transistors were tied to the gate and drain terminals (back-bias) to reduce the effective threshold voltage.
Could this configure work normally?
How to analyse the body-effect of PMOS?
Under this condition, the Source voltage is higher than the nwell voltage,the performance of PMOS must be affected.for PMOS,is the model fit to the condition Vbs<0?
thank you!
The paper will be uploaded later,the details are on the 7th page.
