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It depends on your design style - bottom-up or top-down.
In a bottom-up design style (which is the most common) you are designing the block before you design the top-level that assembles the blocks. In this case you have no information on the signal delay outside the block because it has not been designed yet. So you must estimate a realistic input/output delay with a rule of thumb or some other flow methodology technique.
In the top-down design style, the top-level is designed first and then the block is designed according to specifications handed down from the top-level requirements. In this case you have exact information on what the input/output delays actually are, because they have been designed before you design your block.
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