calculate min clock period

Determine the minimal clock period TW for the following circuit. Use the following delay values for the flip-flops and gates.
Flip-Flop: 5 ≤ tPFF ≤ 14ns; tsu = 6ns; th = 10ns
Inverter: 2 ≤ tPINV ≤ 12
XOR Gate: 7 ≤ tXOR ≤ 22

TWmin = 54ns

In setup we use the slow corner. Trace one of the paths through the XOR (they are both identical) and demand that the signal arrive at the D pin of the first FF 6ns (tsu) before the next clock tick arrives. This gives you:

tPINV + tPFF + tXOR =< TW - tsu
12 + 14 +22 =< TW -6
TW >= 54

Let us now check to see if the hold time is met (note that hold time checking is independent of TW, because we are talking about the SAME clock tick at the launching and capturing FF. Setup uses TWO CONSECUTIVE ticks)

For hold checking we use the fast corner. Trace a path from the launching clock to a D-pin and demand that it not arrive sooner than 10ns (th). The paths through the XOR both meet hold because:

tPINV +TPFF +tXOR >= th
2 + 5 + 7 >= 10 TRUE

However, the circuit will not work because it has hold time violations on all other paths (those not going through the XOR). For example, take the path from the first to the second FF. The signal at the second FF's D-pin must remain steady for 10ns (th) after the clock tick arrives at the second FF.

clock tick arrives at second FF in: tPINV = 2 ns
so the D-pin must remain steady for: 2 + 10 = 12 ns
The D-pin actually changes in tPFF = 5ns
Sinc 5<12 there is a hold time violation