pavan_85
Member level 1
HI FRIENDS,
I am working on QPSK Demodulator implementation in VHDL.
We had used Gardners algorithm (Ij-1/2 *[Ij-Ij-1]) for BIT TIMING Loop.
My doubt is whether to delay my next input signal for 2 clk periods.
Or can i give it after a clk delay(since as per algotithm is force two with a duration
of clk period it might give me a different result).
Regards,
Pavan
I am working on QPSK Demodulator implementation in VHDL.
We had used Gardners algorithm (Ij-1/2 *[Ij-Ij-1]) for BIT TIMING Loop.
My doubt is whether to delay my next input signal for 2 clk periods.
Or can i give it after a clk delay(since as per algotithm is force two with a duration
of clk period it might give me a different result).
Regards,
Pavan
