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    Why increasing transistor size reduces delay in operation of MOS?

    Can someone explain why increasing transistor size reduce delay in operation? Also what is Self-loading effect?

    •   Alt6th August 2008, 11:34

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    Re: About delay in MOS

    Delay in a gate can be simplified as the amount of time it takes to discharge the load capacitance that the gate or fet is driving.

    I= q/t = C*V/t

    t=C*V/I

    1) to the first order, delay (time) is inversely proportional to drive current. So, increasing the drive current will reduce the delay.

    2) Increasing the MOS width will increase its drive current.

    Therefore, increasing MOS width will increase its drive current which will reduce the discharge time of the load ( reduce delay).

    --------
    To answer your next question:
    t=CV/I = (Cload + Cself)*V/I = Cload*V/I + Cself*V/I = Delay_load + Delay_self

    Each fet has parasitic cap (diffusion cap for example: Cself) which contributes to a delay we can call Delay_self.

    One interesting thing to note is that when we increase the MOS width, we not only increase the current drive but also Cself. So, you will find that Delay_self will stay more or less constant though delay_load will reduce.

    There is a lot of over-simplification here, but intuitively this is what is happening.



    •   Alt7th August 2008, 21:34

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    Re: About delay in MOS

    So how do we improve the performance of the MOS...?
    As you have mentioned increasing the MOS width with not alter the performance much...



    •   Alt11th August 2008, 06:23

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    Re: About delay in MOS

    Thts true...Thou increasing the width of a MOS transistor...will increase the current...but Increasing width will also increase the device capacitance which will tend to add to the delay...



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    Re: About delay in MOS

    So how do we improve the performance of the MOS...?
    As you have mentioned increasing the MOS width with not alter the performance much...
    That is not the conclusion to be drawn from my description of delay.

    Below is an equation for the delay of a gate based on logical effort methodology.

    Delay = a*(Cself/Cin) + b*(Cload/Cin)
    = K + LE*fo

    Cin= input capacitance of the driving gate
    Cself = parasitic cap
    Cload= load cap
    a,b are constant for the specific type of gate topology (inv, nand, nor etc)
    LE = logical effort of the gate and is constant for the specific topology.

    Cself/Cin is more or less constant, since increasing gate size will increase both Cself as well as Cin and that effect cancels out.

    Cload/Cin is called the electrical fanout of the gate.

    If you want the delay through the gate to be small, you should make the gate bigger and that would reduce the fanout.

    However, we have to keep in mind that there will be other gates that need to drive Cin. So, we cannot make the gate very big. You cannot size one gate in isolation but you should consider the full chain of logic or gates. Typically, there will be an optimum sizing solution. In the case of a chain of inverters driving a large load capacitance, the optimal electrical fanout is found to be between 3 and 4.

    If you are interested, you should readup more on "logical effort". Its a very simplified but powerful way of looking at gate sizing.



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    Re: About delay in MOS

    When I think about the fastest CMOS I try to think in terms of "Logical effort"

    http://en.wikipedia.org/wiki/Logical_effort

    Where you see you make the total minimum delay be making all the
    logical efforts of the stages the same.(equal to each other)

    google CMOS logical effort. Lots of references.



    Goofy book that I had for EE4xx
    http://books.google.com/books?id=hGV...8B0des#PPP1,M1



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