vikram789
Member level 3
hi, till now i have read that clock skew pose a problem for designers but now i have heard that it can also help by decreasing the clock period .. following two eq. might also help u to compreheand the idea so tht u can explain that to me....
1. T >= reg + path_{max} + S - (s_d - s_s)
2. (s_d - s_s) =< reg + path_{min} - H
* T is the clock period,
* reg is the source register's clock to Q delay,
* pathmax is the path with the longest delay from source to destination,
* S is the setup time of the destination register
* pathmin is the path with the shortest delay from source to destination,
* H is the hold time of the destination register,
* (sd − ss) represents the clock skew from the source to the destination registers,
* sd is the clock skew to the destination register, and
* ss is the clock skew to the source register.
1. T >= reg + path_{max} + S - (s_d - s_s)
2. (s_d - s_s) =< reg + path_{min} - H
* T is the clock period,
* reg is the source register's clock to Q delay,
* pathmax is the path with the longest delay from source to destination,
* S is the setup time of the destination register
* pathmin is the path with the shortest delay from source to destination,
* H is the hold time of the destination register,
* (sd − ss) represents the clock skew from the source to the destination registers,
* sd is the clock skew to the destination register, and
* ss is the clock skew to the source register.