How to estimate and set optimization constraints using DC tool?

1. How to estimate and set optimization constraints using DC tool?

Hi All
I am looking for some help regarding synthesis, i am using the DC tool.
i need to set the constrains, DRC constrains are by set in the tech lib we use.

I need to understand how can i set the optimization constrains( input delay, output delay, and min and max delay,clock uncertinity and latency and false path and multi cycle paths), the inputs that i have for this is , clock frequency of the chip.

Could you pls provide any doc which explains in elaborate with examples about these.

I read DC user guide, it explains syntax of the command to set the constrains, but it doest explain, how we can estimate those constraints

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2. Re: synthesis

Hi,
I have written a tutorial on dc, I guess it will help you.
http://www.vlsiip.com/dc_shell
It gives actual commands used to set constraints, and the page also gives example to set false paths, and much more.
hope it helps,
Kr,
Avi

1 members found this post helpful.

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3. Re: synthesis

Thanks Avi.

I have an idea on the commands to set constraint, but i am looking to know how to estimate those constrains (the inputs are clok frequency and RTL only), means how can i estimate input delay and output delay and clock uncernity, and max delay and min delay for combo paths and other constraints like false path and multi cycle paths
etc..
Thanks

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4. Re: synthesis

Input delay/Output delay: Your object is to find out a register to register path. If a signal called A_to_B, originates from a blcok A and goes in block B, that is to say, that the signal A_to_B, comes out of a Q output of a register inside a block A and goes to D input of a register in block B, then the total allowed delay for this signal from Q to A is clock period, say TCK_period(ignoring clock skew, setup time, and signal propogation time).
Now the path looks like:
Q->Output port at block A(OP_port_A) -> input port at block B(INP_port_B) -> D
Now the output delay on OP_port_A will be TCK_period - delay from INP_portB to D in block B
and the input delay on INP_port-B will be TCK_period - delay from Q to OP_port_A in blcok A
Got the picture? Similarly you can work out for combi paths through your block by getting the origin and the final destination of the path.
This is idealized case, you may need to put in the values of clock skew, setup time, signal propagation time form Block A to Blcok B as well.
False path/multicycle path: Its the designer who knows it and he must supply these to the person who is synthesizing the block.
Hope it helps,
Kr,
Avi

1 members found this post helpful.

5. Re: synthesis

Thanks Avi

Added after 1 hours 56 minutes:

Thanks

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