Input delay/Output delay: Your object is to find out a register to register path. If a signal called A_to_B, originates from a blcok A and goes in block B, that is to say, that the signal A_to_B, comes out of a Q output of a register inside a block A and goes to D input of a register in block B, then the total allowed delay for this signal from Q to A is clock period, say TCK_period(ignoring clock skew, setup time, and signal propogation time).
Now the path looks like:
Q->Output port at block A(OP_port_A) -> input port at block B(INP_port_B) -> D
Now the output delay on OP_port_A will be TCK_period - delay from INP_portB to D in block B
and the input delay on INP_port-B will be TCK_period - delay from Q to OP_port_A in blcok A
Got the picture? Similarly you can work out for combi paths through your block by getting the origin and the final destination of the path.
This is idealized case, you may need to put in the values of clock skew, setup time, signal propagation time form Block A to Blcok B as well.
False path/multicycle path: Its the designer who knows it and he must supply these to the person who is synthesizing the block.
Hope it helps,
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