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What's the differences between the two level shifter?

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siboy

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The second level shifter add two PMOS in the middle. In my thought, the two PMOS in the middle should use smalles MOSFETs. But I don't understand why to add the 2 PMOS? Does it have any advantages? And which situation we'd better select the second level shifter?

Thanks!
 

the level shifter is a nothing but a source follower .The output impedance of it should be less.Hence cascoding reduces the output impedance by a gm facto r
 

Also the second one uses postive feedback ( non linear) so it can operate at h
higher frequency
 

1.source follower? kind of weird, i dont think level shifter works under saturation region. It's more like a digital cell, with its node voltage switching between VDD and 0v.

2.positive feedback... nah, the first one IS a positive feedback circuit too.

3.My opinion is, the second lv shifter will have much less leakage current from VDD to gnd.

look at the left side of the 1st circuit.
if you send a clock signal at vin,
the pmos at left top(say MP1) and the nmos at left down(sayMN1) would conduct at same time,and a huge current will flow from VDD to GND. you can run transient simulation, and probe I(MP1) and I(MP2) .

for the 2nd circuit ,now we have MP1,MP2,MN1 at left side(from top to bottom). Even a clock signal at Vin,these three mos are almost unlikely to turn on at same time, so there wont be a direct current path from VDD to GND.

This helps to reduce current consumption,especially when you use a lot of clock drived lv shifter in your circuit.
 

Thanks, patato
For 1 and 2, I agree with you! Not a source follower. It's a level shifter for digital circuits. The upper PMOSs in both level shifters are latch transitors, so they must be positive feedback.
For 3, I think the in 2nd shifter 3 MOS in one side may also turn on at same time as the the 1st shifter(The time in both shifters is short). But the current may much less for the PMOS in the middle. So I think the PMOS in the middle should use small W/L PMOS.

Does the 2nd level shifter have othe advantages? Such speed?
 

well, i dont think it gives any advantage with speed. Just reducing power i guess.
 

Guys Guys

i would like to clarify my doubt as well answer

The second circuit uses CMOS instead of a PMOS or NMOS
So it has all the advantages of CMOS associated with it

Its true my friends it is a Digital Level Shifter


Correct me if i m wrong
 

My opinion:

The top two PMOSs is actually a latch, just like two digital inverter connected head with tail (in Chinese, you know?!). We know that the drive ablity of one inverter must less than the other, so that the latch can be trigged.

Here, if you use the first shifter, when the input drive is weak, or the difference of two VDD is big, it may not be trigged when the input change. However, the second one will, since the current path from VDD is cutted or half-cutted by the added two PMOSs.

Only my OP..
ELE
 

I agree with leehying.
By the way, Level shift is also a comparator or amplifier during the changing process! Larger gain, larger resolution and faster speed.
 

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