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Problem with a I2C slave circuit simulation

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ise_lewis

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My design is I2C slave circuit, it latch data by pos-edge of SCL and output by neg-edge of SCL. I run simulation post-synthesis with Modelsim, it is ok. And then I generate cdl file from nestlist with CMOS models, but when I run simulation with HSPICE, it is wrong.

When it send ACK bit , SDA change low to high at post-edge. So the circuit can not work. I dont know what problem with the circuit. Please help me.
 

I2C problem

Sounds like a timing violation, but it's ony a guess without knowiing the circuit.
 

Re: I2C problem

what is the frequency of you cirsuit run? can you check your design in the Post-Simulation with max frequency? may be it can't work with it!
 

Re: I2C problem

run at 100KHz - 200Khz. It is not quick.
 

I2C problem

The analysis should allow to recognize, why the circuit is failing, respectively which logic cell is behaving different from ModelSim analysis. Because of the required dual-edge sensitivity, the circuit has to be designed as a combination of synchronous and asynchronous logic. There are many possible traps in this kind of design.
 

Re: I2C problem

I think the causes :

1. Timng constraint, How to constraint dual-edge clock of I2C?

2. I2C Pad, anyone give me a schematic of a I2C pad with ESD?
 

I2C problem

You can design a logic with a dual-edge, the ModelSim don't cry about it but it is then sure non-synthesizable.

Use just one clock, for example negedge SCL, and design some asynchronous logic [with "assign" statement, if I remember correctly...] which generates the other synchronization possibilities, if you need them.

+Krivan
 

I2C problem

you ACK should change at negedge sclk after TDH,
it should last one clock cycle, your waveform why only half cycle?
 

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