vishwa
Banned
rtl simulation with timing
Hi,
I have better knowledge in RTL design in using Verilog/VHDL. Worked in multiple projects.
But I am very new to functional simulation of RTL description. I have few questions on how design a testbench setup.
1. What are the considerations while designing testbench.
2. How to check the internal signals of a design
3. How to check the full functionality of a RTL design, if it has multiple functionalities.
4. What is timing simulation. How come it ispossible to check timing at RTL design level. I think timing can be verifed once the gate netlist is generated.
Please help me in this regard. Please let me know is there any book/tutor to learn about the RTL simulation.
Thanks in advance,
Viswa
Hi,
I have better knowledge in RTL design in using Verilog/VHDL. Worked in multiple projects.
But I am very new to functional simulation of RTL description. I have few questions on how design a testbench setup.
1. What are the considerations while designing testbench.
2. How to check the internal signals of a design
3. How to check the full functionality of a RTL design, if it has multiple functionalities.
4. What is timing simulation. How come it ispossible to check timing at RTL design level. I think timing can be verifed once the gate netlist is generated.
Please help me in this regard. Please let me know is there any book/tutor to learn about the RTL simulation.
Thanks in advance,
Viswa