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How to improve the SINAD of a transmission gate?

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Prasanta

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Hi,

I am running SINAD simulation for my switched cap filter. The acceptable lower limit is 25 dB. I am getting value close to that. Even with ideal amplifier it is not improving much.

So I am just trying to check SINAD for transmission gates used for switching the capacitor. So now in the test bench I have four switches and a capacitor (that is euivalent a resistor) and a capacitor, i.e , so a low pass filter basically. But this simple configuration gives me SINAD less than 25 dB. And I have tried differnt input signal magnitude.

Could someone give me advice how can I improve the SINAD of transmission gate.

Thanks and Regards,

Prasanta
 

SINAD improvement

If your capacitor is a passive one, this could be a charge injection case. Use bottom sampling and fully differential architecture to reduce it.
BTW, MOS model parameter will also affect the charge injection simulation, but it's only simulation case.
 

Re: SINAD improvement

Thanks for the reply.

Yes I am using passive capacitor. But I am using differential mode.

You said this might me because of MOS model, is it possible to check that? Could you please elaborate.
 

Re: SINAD improvement

Prasanta said:
Thanks for the reply.

Yes I am using passive capacitor. But I am using differential mode.

You said this might me because of MOS model, is it possible to check that? Could you please elaborate.

I think further analysis may need your circuit diagram.

Generally, beside fully differential, bottom sampling is also important, have you checked that your switch on bottom plate of cap will be off earlier than the top plate switch off? Also the hold phase on must be later than bottom sampling off and no overlap.

Another concern is the ratio of your switching MOS to the sampling cap, if it is too large, the charge injection is hard to avoid, and if it is too small, the RC is comparable to the sampling period is also disaster.

For model parameter XPART, if you circuit is propriate, it need not to be considered before your THD reach about -50dB in simulation.
 

Re: SINAD improvement

Thanks again,

my clock frequency is 8MHz and I checked the clock overlap, it is 10psec. Do you think this tiny overlap can make SINAD so poor?

as MOS size is concerned, it is not that large, I mean its effective capacitance I have taken into account when put my passive capacitance. And I did check, the capacitor is discharging properly, and I checked the RC time ocnstant. They are all fine.

regarding XPART, I found it is =1 for the MOS model, I found in the internet it means drain/source charge sahring 0/100........ Do I have to change my SINAD programme so that it give me right result?

or do I have to make XPART =0?
 

Re: SINAD improvement

Prasanta said:
Thanks again,

my clock frequency is 8MHz and I checked the clock overlap, it is 10psec. Do you think this tiny overlap can make SINAD so poor?

as MOS size is concerned, it is not that large, I mean its effective capacitance I have taken into account when put my passive capacitance. And I did check, the capacitor is discharging properly, and I checked the RC time ocnstant. They are all fine.

regarding XPART, I found it is =1 for the MOS model, I found in the internet it means drain/source charge sahring 0/100........ Do I have to change my SINAD programme so that it give me right result?

or do I have to make XPART =0?

1> Clock need to be proven non-overlap by logic, usually at least 1~2 gate delay(0.1n for 90nm or .13um) and make sure not eaten up by wire delay. 10p is too small and may be a reason. Suggest you to make your top plate off and hold phase 0.1~0.2n later than bottom off.

2> You can trace voltage across your switch, if it's only several mV, than XPART=0 may be more suitable.
 

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