multicyle and false path in asic Design

asic multicycle path for different clock domains

Hi All,

How to identify the Multi cycle path and the False path in the design. do we need to identify after the Synthesis stage DC tool it self will recognize and through as warning or error.

At what stage in the asic flow this multicycle path and False path are identified. How to fix this Multi cycle path and false path in the asic fpga flow

How it is going to effect the Timing Closure and the Slack of the design.


regards
kil

false path

Hi,
As per my experience i feel synthesis tool might not give out any multi-cycle/false paths.
We need to identify the multi-cycle and false paths, as per design and specify them to tool.
Generally paths crossing clock domains are specified as false paths to the tool so that the will not waste time in analyzing those paths for timing. We can specify multi cycle paths by design if there are any, which will improve the tools efficiency in analyzing the timing. Also we can check any critical timing paths are multi cycle paths and specify them to the tool.

Thanks,
RamaMohan Rao K

asic false path

There is no automatic way to create a complete list of false paths and multicycle paths. The designer needs to list them for the timer.

I think Fishtail (https://www.fishtail-da.com/) tries to provide an automatic tool, but I'm not sure how complete its coverage is.

Keep in mind that for most EDA tools, the more timing exceptions you specify , the slower the tool runs.

The practical solution that everybody uses is to list all the false/multicycle paths that you know of and then run a timing report. If timing is OK, everything is fine. If there are timing failures, check to see if any of them are false/multicycle paths. If yes, then those timing failures are false and you need to add them to the exception list. If none of your timing failures are timing exceptions, then you have a real timing problem.

asic false-path

Marc,
w.r.t EDA tolls in your reply you mean to say that, adding false/multi-cycle paths will make the tools run slower. If yes please justify that?

specifying clock to clock false paths

Hi kil:

Yes it slows down the STA timer. Every timing exception is an additional rule that must be added to the basic STA algorithm. And each one requires CPU time to check which slows down the tool. A handful more or less doesn't make any difference, but long complex lists of timing exceptions are a drag for most tools. I cannot vouch that this is true for every last tool, but it is true for many EDA tools, including P&R.

Keep in mind that you must absolutely specify all significant timing exceptions or the optimization tool will focus on trying to fix spurious timing problems. But it is not desirable nor possible to list all the exceptions exhaustively.

If a timing exception, for example, a false path does not cause any timing violations then we don't care if the P&R tool does some minor bit of unecessary optimization to optimize this false path.

So you only need to list those exceptions that would otherwise rise to near the top of the critical path list. Unfortunately these can usually only be identified through trial and error.

design compiler multicycle

Can somebody tel me how do I decide on multicycle path ?

Lets take an example: I need to derive constaints at the top level ( chip/SoC level)
I have a path running from one IP-block to another IP-block then how do I know that this path is a multicycle or not ?

Thanks.