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  1. #1
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    ddr2 length matching

    Hi all,

    Can any body explain the skew relationship between DDR2 Clock signal and DQS signal.

    Is there any length matching requirement for these two signals?

    •   Alt10th July 2008, 08:19

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    dqs signal for ddr2

    Hi,

    In DDR2 routing, u have to 3 types of lines

    Databyte lanes
    Address and command lines
    Clock lines

    Each databyte lane include 8 databits(DQ0:7), 1 DataMask(DM0), 1 Data strobe(DQS0).
    For a single byte lane, u should consider DQS as the clock and route them with 100mils tolerant length matching. like wise, u do for all the bytelanes.

    Route address and command lines with length matching with 100 mils matching tolerance.

    route clock as separate with 20mils matching betwwn the differential pairs.

    There is no need to match the DQS and clock lines.

    Regards,
    sandhya
    Route



  3. #3
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    ddr2 dqs and clock skew

    Hi ......

    I am working on a motherboard...

    and found that there should be only 25 mils mismatch between data lines and DQS0

    and DQM0.



    •   Alt16th July 2008, 10:15

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  4. #4
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    from dqs to clock

    Quote Originally Posted by pcb87
    Hi ......

    I am working on a motherboard...

    and found that there should be only 25 mils mismatch between data lines and DQS0

    and DQM0.
    How much length difference u have between DQS and Clock



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    routing lanes ddr2

    In my design, according to the guidelines clock length is between 2 inch and 7 inch.
    and i routed all the colock signals as differntial pairs in 80mm length.
    I think there is no need to match the length of the clock signals and the DQS and DQM..
    these are routed with MD[0:7] data lies.
    and mismatch should be less than 25 mils.



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    ddr2 routing lenghth

    hi pcb87 r u using SODIMM or Discrete components?



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    relation between dqs and clock in ddr2

    I am using DDR2 DIMM.



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    ddr2 clock

    hi i am simulating ddr2 clock in hyperlynx but the ibibs model of soc is single neded.Is it copulsary that clock should be diferential.\and also the clock is not coming proper.



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