Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

calculating power consumption for ideal conditions

Status
Not open for further replies.

snr_vlsi

Member level 1
Joined
Jan 21, 2008
Messages
34
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
1,564
pwr consumption

Hi,

If the power consumption value is 3 W reported under worst case conditions, what can be the pwr consumption value that can be assumed under ideal conditions for power planning.

Thx

snr_vlsi
 

Re: pwr consumption

Power consumption of what? An analog circuit? a digital chip? what?

Also what do you mean by "worst case conditions"? Do you mean worst case process-voltage-temperature, or do you mean worst case activity (i.e.: everything on the chip is active at the same time). Remember, all power analysis is very heavily dependent on the activity of the circuit, and any change in the circuit activity will have a much, much greater effect than any PVT change.

Need to be more specific.
 

Re: pwr consumption

HI,

By worst case condition, I mean everything on the design is switching. Moreover the design is digital.

I derived the pwr consumption of 3 W using DC through setting switching activity.

Thx

snr_vlsi
 

Re: pwr consumption

The degree to which your total power will change if you change the activity is very circuit dependent. I don't think you can give a general guideline. Some circuits show a huge power difference between 'fully active' mode and 'quiet' mode, others show only a small difference. It's not as if all circuits have a common behaviour in this regard.

It is also important to consider if you have added clock gating or not. Without clock gating, every flip-flop will toggle and use power at every clock tick - even if the circuit isn't doing anything. With clock gating you can block the clock signal from reaching the flip-flops if they are not changing their state. This saves a lot of power depending, once again, on your activity.

A second important thing to consider is that Design Compiler (DC) does not see the clock distribution network because clock tree synthesis (CTS) has not been run yet. So your 3W number is not correct. Typically the clock tree buffering will consume as much power as the flip-flops themselves. The clock distribution network is the single most important net in the design for power, but you are ignoring it at the stage DC runs. So don't put too much faith in that 3W number.

Sorry I can't give you a simple answer, but power consumption is hugely variable and there is no general answer to your general question
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top