Ringing between power clamp and package parasitics

how to avoid ringing due to bond wire models

Hi all! I am having problems trying to simulate a very simple circuit; I hope someone can give me a hint on what's going wrong. Basically, the (equivalent capacitance of the) ESD power clamp protecting my chip is oscillating with the parasitic inductance of the package and pins that connect it to the power supply!!! :!: Please let me explain a little...

I am trying to simulate in Cadence a very simple binary transmitter consisting basically of just one output buffer. I am specially interested in taking into account in my model the parasitics of the ESD protections, the wirebonds and the package, so as to analyze effects like the power and ground bounce that occurs when the buffer commutes. The circuit can be sketched as shown in the following figure:

The chip internals consists of the output buffer, some logic, and the ESD protections: a grounded gate NMOS (ggMOS) protecting the output pad, and a power clamp between the internal vdd and gnd lines. The figure also shows the external connections of the chip to the power supply and the communication channel, where the inductances "Lp" model the parasitic inductances of the wirebonds+package interface. In my model, Lp=5nH.

When the output buffer is idle, the circuit works fine. The problem occurs when the buffer commutes from '0' to '1' and draws current from the power supply. Just at the beginning of such a transition, the situation is as shown below:

Notice that in the previous figure the power clamp has been replaced by an equivalent capacitance Cclamp (=300fF in my 0.35um technology) and the logic has been omitted for simplification (just a few gates drawing little current). As expected, upon transition the buffer starts to sink current, and since the power supply cannot instantly provide it (because of the inductances Lp), the current is almost entirely provided by the power Clamp capacitance. I find this very weird (the clamp supplying the circuit?), but at least it is physically possible in principle.

However, the worst thing is yet to come. Just after the first instants upon the buffer transition, the power supply starts to provide current to the circuit. What my simulations reveal is that part of the current entering the chip is the power supply feeding the buffer and another part is the inductances Lp resonating with Cclamp!!! What's worse, even after the buffer finishes its transition and stops sinking current, the Lp's continue to oscillate with Cclamp, with virtually no damping!. As a result, the voltage drop on the inductances Lp also oscillates, producing horrible power and ground bounces on the internal rails of the chip, as shown below:

MY QUESTION(s) IS(are): What's wrong with this model??? As far as I can see this problem should happen to any circuit drawing current from the supply, not just my particular buffer. In fact, if in my simulation I remove all my internal circuitry and just connect some commuting inverters from the vendor's standard cells, I observe the same ringing. Connecting bypass capacitors in parallel with the supply doesn't help to eliminate/damp the oscillations, it just varies their frequency...

...How does real circuits (which must for sure have power clamps between vdd and gnd and parasitic inductances from the package and the wirebonds) cope with this issue?

I can only think that the model of the clamp is not correct, but I am taking it from the vendor's design kit, which provides front and back-end views. Also, if I replace the clamp with an equivalent 300fF cap, I get the same results. After all, under normal operation the clamp should only behave as some parasitic capacitance, right? What I am missing here?

WELL, THANKS SO MUCH IN ADVANCE FOR ANY HELP/IDEAS/COMMENTS. Sorry for the long post; I am really desperate to figure this out...

Regards,

Jorge.

0.8nh/mm

Hello Lagos.ji,
The problem with your model is that there is no parasitic bond wire resistance or even metal resistance. Even a small amount of resistance would make the difference. Another thing you might want to double check after adding the parasitic resistance is to check the value of the bond wire inductance - it seems a little high to me but I may be wrong since it would depend on the bond wire and your bond length. Hope this solves your problem, it did for me when I saw same oscillations.

Ground bounce actually exist in a real circuit, but I also think that Lp should be lower. Also a resistive component should be considerered, but the supply bonds may act almost inductive in the interesting frequency range. What's the package type?

aryajur said:

Hello Lagos.ji,
The problem with your model is that there is no parasitic bond wire resistance or even metal resistance. Even a small amount of resistance would make the difference. [...] Hope this solves your problem, it did for me when I saw same oscillations.

Click to expand...

Hi Aryajur! thanks so much for your reply. What could be a typical value of the series resistor that I could add in order to model the resistance of the loop and avoid the oscillations? Or even better, do you know of any reference (book, paper, etc.) that deals with this "problem"?

Thanks again for your help!

Added after 7 minutes:

FvM said:

Ground bounce actually exist in a real circuit, but I also think that Lp should be lower. Also a resistive component should be considered, but the supply bonds may act almost inductive in the interesting frequency range. What's the package type?

Click to expand...

Hi FvM! thanks for your interest. I am considering a plastic quad flat pack package. I have seen in a real extracted model that Lp is in the order of 3.5-4nH, but my advisor said to use 5nH to account also for the wirebond and to be on the safe side... do you happen to know of any reference (book, paper, etc.) that mentions how to appropriately model/cope with this problem?

Thanks in advance for your help!

Regards,

Jorge.

hello Lagos.ji,
You don't need to look this up from a book. The packaging information from you resource should provide you the resistance of a bondwire per unit length. Add that to your bondwire model on series with the inductance. This is simply the metal resistance so will be quite small but would damp out your ringing sufficiently. You should also add some estimated worst case metal resistance of the traces you will put in the layout.

A series resistance of e. g. 0.05 ohm may be suitable first guess. The pin inductance and resistance values for a specific package should be given by the manufacturer. Exactly viewn, they are different for each pin, depending on the lead frame geometry and bond wire length. If no manufacturer data are available, a free tool as Fasthenry (www.fastfieldsolvers.com) can calculate the self and mutual inductances and resistances very accurately, but you have to know the geometry.

Hi aryajur & FvM! ...After experimenting a little with the circuit I've come to some results; I would be really grateful if you could please give me further advise.

I checked the data relative to the package I am considering, and found that Rpackage+Rwirebond should be approximately 0.1ohm. However, the inclusion of this resistance in the model of the power loop dampens the oscillations just a little, and at the frequency in which I am working (100MHz), it's not enough to make them vanish in a clock period. Also, the bounce they cause in the power lines still seems too large to me: +-200mV.

Then I discovered that by adding a 1pF decoupling capacitor IN PARALLEL with the power clamp the amplitude of the bounce decreases to +-80mV, but the damping is also reduced. If I use 10pF the bounce diminishes to +-40mV, but the damping is so low that it almost appears as a sustained oscillation!

So finally I considered some output impedance for the power supply. By adding a 50ohm resistor in series with the external power supply the oscillations dampened completely, and the total overshoot maintained around +-40mV. However, in all the literature that I have read about output buffers and switching noise, I have never seen anyone to consider the output impedance of the power supply! This really puzzles me, because whatever the type, the real power supply will have a non-zero output impedance, right? I started to wonder why nobody seems to include it when dealing with switching noise...

So the questions are...

-Is the usage of a on-chip decoupling capacitor between the internal power buses a common practice for dealing with this type of oscillations? If so, what are common values used for these capacitors?
-Is the inclusion of a non-zero resistive output impedance for the power supply a sound assumption? If so, what value of output resistance could be representative? This chip is thought to "live" in a standard PCB and be powered by common off-the-shelf regulators along with other circuitry...

Thanks again for you help!

Regards,

Jorge.

Hi all; I still haven't been able to figure out this one... any help is welcome and really appreciated

Regards,

Jorge.

lagos.jl wrote
....I have never seen anyone to consider the output impedance of the power supply! This really puzzles me, because whatever the type, the real power supply will have a non-zero output impedance, right? I started to wonder why nobody seems to include it when dealing with switching noise...

But you know that they should. Such a circuit is definitely going to ring. If the total series resitance of the power/output loop does not provide sufficient damping, then that is simply the case, and ringing will occur. (If the behaviour is not in accordance with calculation, then there would perhaps a mystery.)

I think that you have largely answered your own questions

In practice, the supply's impedance will be much higher than the of the package alone. A typical 3-pin regulator will have some capacitance placed at its output pins, often a tantalum bypassed with a ceramic. Say, 10uF//100nF The ESR, and that of the PCB traces and returns, should be modelled.

Designers will add the ubiquitous 100nF bypass cap, needed or not. There will also be pcb and other resistances in the output circuit that will limit the instantaneous current demand, so perhaps your model is unrealistic in this area.

Rarely does one see oscillation of the supply loop, because the resistance is usually high enough to prevent it. The oscillation in such drivers will more often be local, such as between the package and the nearest 'bypass' capacitor or reactive load.

Thanks a lot for the reply, Humber. In my case, modeling the switching noise -whether it be of oscillating nature or not- is one of the main goals.

Would it make sense to model the entire system in Cadence using perhaps a Spice model of a real voltage regulator, in order to take into account the impedance of the power supply? One colleague of mine told me that any real regulator would show near-to-zero output impedance at DC, but at the frequency of the oscillations I am seeing it would show a *very* large impedance, which would prevent that ringing to occur in reality. Thus using a Spice model of a real voltage regulator instead of an ideal DC power supply would solve my simulation problems...

Any other ideas are really welcome!

Hello lagos.jl,

The voltage regulator will have little effect at such high frequencies. For all practical purposes, it will be de-coupled from your circuit. The oscillating currents will simply circulate through the regulator's output capacitors, damped by their ESR.

If the regulator and its capacitors are remote from the package pins, then the PCB trace inductance will come into effect. The rule of thumb for trace-over-ground-plane is 0.8nH/mm, though this can vary considerably.

As you clearly understand, series damping must be in this loop to be effective, but sometimes parallel resistance is added close to the package, usually with a series capacitance to reduce the static dissipation( i.e. a snubber).

An accurate model will need to include the pcb trace impedance and the ESR of the capacitors. Kemet has a useful programme that models their capacitors .

In practice, one hopes that the layout is good, and the ESR enough. If not, then it's out with the snubbers and ferrite beads !