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How to verify the pattern in TMAX ?

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binbin1994

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in TMAX, after ATPG, how can I verify that the pattern is work or not?

use the " Simulation" or "run fault_sim" or both of them?

they are only verify the pattern's logic?

do i need to creat the verilog-environment to run the post-sim to verify the pattern ?

thanks!
 

Re: TMAX's questions

Hi binbin,

You can verify the pattern in Tetramax with just run_sim. But I will not be contended with the results of Tetramax. The reasons are

* Tetramax created the pattern and now you are asking it to verify. So, if it has done some wrong assumption during generating the pattern then it will use the same assumption while validating it .

* Tetramax does not takes timing in account

So to really verify the patterns simulate it in a simulator. (VCS etc...)

-cheers
vlsi_eda_guy
 

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    binbin1994

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