Please tel me how to debug following synthesis error Verilog

synthesizable verilog debugging

ERROR:Xst:528 - Multi-source in Unit <defer_count> on signal <txc>
ERROR:Xst:528 - Multi-source in Unit <defer_count> on signal <x_busy>

Please tell me what changes should i do in my code(RTL simulation logically OK) so that code becomes synthesizable.

Your code has multiple outputs connected together. Probably two different statements simultaneously driving the same signal.

If you need help locating the problem, show the HDL code.

Seems that you're moving a signal from 2 different source.
For example you've 2 process that move txc and x_busy.
Example counter.

p1rocess(clk)
begin
if clk'event and clk ='1' then
.if a = '1' then
..cnt <= cnt +1;
.end if;
end if;
end process;

p2rocess(cnt)
begin
if cnt = 255 then
.cnt <= 0;
end if;

that example has 2 important error. first is the ine you've in your project and the second one is that the rst on cnt is asyncronous.

You've to correct it in this way.
process (clk)
if clk'event and clk = '1' then
.if cnt = 255 then
..if a = '1' then
...cnt <= x"01";
..else
...cnt <= x"00";
..end if;
.else
..if a = '1' then
...cnt <= cnt + 1;
..end if;
.end if;
end if;
end process;

Hope that it's clear.
cu

PS. remove the "." I've put it only to make retain a bit of formattation (here on the web it's removed all the space, I don't know why)

Re: Please tel me how to debug following synthesis error Ver

Thanks to both (echo47 and mmarco76
)
,your advice worked.