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Help with Virtuoso PLEASE, have very strange problems vdd!

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gezzas525

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As i described in a previous post now when placing pins, for example the invertor, I placed an IN, OUT vdd! and a gnd! I DRC and extract the design OK. Viewing the extracted layout the nmos transistor is the wrong was round. Now when when it comes to simulate I have to specify the IN the vdd! and gnd! however they are not under global nets but under inputs. Leaving the gnd input as it is and setting IN and vdd! gives me an error as follows

fprintf/sprintf: format spec. incompatable with data -nil

however using any name for the supply without the exclamation mark works fine and I obtain simulation results.

does anyone have any ideas, iam beginging to think that it could be an OS/library issue?


KLEOS
 

Re: Help with Virtuoso PLEASE, have very strange problems vd

OK the problem looks like, the vdd! rail in the layout is not a global even though it has the " ! " , same with the gnd!, the simulatoronly lists it as an input and there are not any global nets.

So how do I rectify this, all the tutorials ive seen use vdd! and gnd! and there fine.

KLEOS
 

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