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  1. #1
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    I need L-edit TANNER software

    Hello,

    I need L-edit TANNER to implant design rules for technology MOSIS,process TSMC 0.18m CMOS.
    Thank you for your help.

  2. #2
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    l-edit tanner

    You can download the free student vision from the Tanner website.



    •   Alt14th June 2008, 11:03

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  3. #3
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    tanner l edit

    i downloaded Tanner Version 12.12 DEMOS that is for TSMC process 0.25m.
    But i want another version for TSMC 0.18m.
    is there any webs ?
    thanks a lot for your help.



    •   Alt14th June 2008, 12:50

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  4. #4
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    l-edit

    Tanner v13 support 3D layout extract ..

    but SPR still use EDIF
    no verilog netlist input Place& routing



    •   Alt19th June 2008, 05:11

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  5. #5
    Member level 4
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    l-edit tanner download

    Tanner v13 support 3D layout extract ..

    but SPR still use EDIF
    no verilog netlist input Place& routing
    I don't understand :'' SPR still use EDIF no verilog netlist input Place& routing''
    thanks a lot for your help



  6. #6
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    tanner l-edit download

    I've downloaded tanner tools v12.
    but, it is very very limited.

    and about design rule, I think it is a lil bit hard to get.
    coz it is some of confidential.



  7. #7
    Member level 4
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    tanner l-edit

    Thanks for your information
    but in our life especially in the field of scientific research there is no confidential things.and if you are true,why we communicate with forum ?
    Also 0.18 m is not a new technology.
    I am a researcher at the laboratory microelectronic in the Faculty of Sciences ,if you have any question ,just write.



  8. #8
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    download tanner tools

    as I remember , in Linux eda enviroment (RHEL) , we usually use Laker /Virtuso ., we never use Windows base layout tool , Tanner can be use just for small company or student ,

    many foundry (Fabs) support DRC/Lvs command file only dracula/calibre or tech file , not for
    ledit , you need write it by yourself , just like Korea EDA mychips ( windows OS base fully layout tools just like Ledit)

    in cell base design (digital circuit design) , we only use "verilog netlist "

    from RTL -> logic synthesis (Synopsys tool) ->
    gate level verilog netlost

    and P&R in Linux workstation , usually > 100K gate
    , ledit SPR not support "verilog" netlist .
    maybe some tool can convert Verilog-to-EDIF
    but , I hope Ledit SPR can support verilog format in the future .



  9. #9
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    l-edit student version download

    Is there any way to download L-edit, from rapidshare or something?


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