clock data recovery (all digital)

Hi all,

anyone can give me all digital clock data recovery circuit for Gigabit rate, with BER of 10e-12

I think it depends on your spec. Different application have different CDRs... I have worked on two projects CDR so far. And as far as I can see, they carry the following similar style:

analog output of clock running at Gigabitrate/data_width; and parallel data of data_width.

Data need to be shifted to match the symbol. shift the bits for each lane;

Data decoding. Depends on your spec. Many application use 10b8b decoding or TERC4 etc. parrallel data is now with width decoded_data_width.

Lane alignment. Use key codes to shift the lane data so that they are aligned. You need a couple of small fifo here.

data de-scrambler. if desired...

data recover block. to separate data stream into control, useful_data etc.

ecc block and other encryption block...

hi fpga_asic_designer

thanks,

Ok my specs are BER of 10e-12, 0.4UI of jitter.

Can you tell me how was your cdr? was it having any frequency correction? apart from phase?

Thanks

There are some IEEE papers which talk about this topics. You may google it then ask for thoses papers on the forum.

Hope it helps