Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Do we need to simulate post synthesis verilog file ??

Status
Not open for further replies.
A

arunjatti

Newbie level 6
Joined
Mar 20, 2007
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,362
synthesis in verilog in xilinx

Do we need to simulate post synthesis verilog file ?? If so how ??? In which tool we should simulate this , cos when Im simulating the .V file in Xilinx it is showing errors ??
In Xilinx only do we need to add any library related to Design compiler
Thanks in Advance
Arun
 

how to use dc to do synthesize

You will need Xilinx primitive libraries like unisim and simprim libraries.. download and install simprim libraries from xilinx website..

Post synthesis XST will generate a Verilog file with all gate level primitives and a sdf file.. use these to do Post synthesis simulation, STA...
 

modelsim gls

Use DC-FPGA compiler to synthesis xilinx lib for your design.
Simulation is must even after synthesis.
If you don't want to do functional simulation by modelsim/vcs/nc-sim.. U can go for formal verification by cadence LEC or SNPS formality..

Thanks
aravind
 

icarus synthesis example tutorial

u can use modelsim or ncsim to perform STA or GLS
 

xilinx icarus

Asicganesh ... STA is not performed by ncsim or modelsim..
Dont post wrong information..

Thanks
Aravind R
 

simulate synthesized circuit or design

Oops! sorry use PT for STA thanks aravind for the correction
 

isdf verilog

hello all,


Thank you for your responses, Im in the ASIC, the prob is with .v file generated with SNPS DC , I want to simulate the file to check the functionality of the design after being mapped to 180 nm library,

I took the same .v file and simulated in Xilinx , but it is not simulated,
So, where should I simulate this file, It is showing error in Xilinx ...Im unable to verify the .V file, I need to verify this .v file so that i can go for placement and routing
Thanks in Advance
Arun
 

xilinx post-synthesis simulation

Hi aunjatti,

the prob is with .v file generated with SNPS DC , I want to simulate the file to check the functionality of the design after being mapped to 180 nm library,
Click to expand...

You can't use this .v file. Because you have synthesized your verilog RTL to ASIC library and
now you are trying to simulate in FPGA environment (Xilinx).

FPGA lib and ASIC lib are two different technology lib.

The only way to simulate your synthesized circuit is use verilog simulator to simulate it.
Thus, the basic input to ur simulation environment are 180nm tech lib, synthesixed circuit (.v) and ur testbench. Your verilog simulator can be VCS, NCverilog, ModelSim or VerilogXL.

Good luck.
 

syntheis, sta and verilog

yes, you should input your netlist with one simulator: modelsim,ncsim,vcs!
 

verilog post synthesis

In ASIC design, Icaus Verilog just performs RTL simulation, could not do GLS with timing delay. You should use a plug-in tool to integrate to Icarus, e.g. iSDF plug-in but too old version!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top