about a counter program

recently i wrote a counter program,i compile it and successful.But when i started to run function simulation,the results were wrong.i do not understand,please everybody who know it give me some advices about it.thank you very much.
here is the code:
module counter(clk,reset,hour,min,sec);
input clk,reset;
output[7:0] hour,min,sec;
wire [7:0] hour,min,sec;
always@(posedge clk or posedge reset)
begin
reg[7:0] hour1,min1,sec1;
if(reset==1)
begin
hour1[3:0]<=0;
hour1[7:4]<=0;
min1[3:0]<=0;
min1[7:4]<=0;
sec1[3:0]<=0;
sec1[7:4]<=0;
end
else if(sec1[3:0]<4'b1001)
begin
sec1[3:0]<=sec1[3:0]+1;
end
else
begin
sec1[3:0]<=0;
if(sec1[7:4]<4'b0101)
begin
sec1[7:4]<=sec1[7:4]+1;
end
else
begin
sec1[7:4]<=0;
if(min1[3:0]<4'b1001)
begin
min1[3:0]<=min1[3:0]+1;
end
else
begin
min1[3:0]<=0;
if(min1[7:4]<4'b0101)
begin
min1[7:4]<=min1[7:4]+1;
end
else
begin
min1[7:4]<=0;
if(hour1[7:4]<4'b0010)
begin
if(hour1[3:0]<4'b1001)
begin
hour1[3:0]<=hour1[3:0]+1;
end
else
begin
hour1[3:0]<=0;
hour1[7:4]<=hour1[7:4]+1;
end
end
else
begin
if(hour1[3:0]<4'b0011)
begin
hour1[3:0]<=hour1[3:0]+1;
end
else
begin
hour1[7:4]<=0;
hour1[3:0]<=0;
end
end
end
end
end
end
end
assign hour=hour1,
min=min1,
sec=sec1;
endmodule

Are you using SystemVerilog? That module won't compile in Verilog because this statement can't go inside an 'always' block:
reg[7:0] hour1,min1,sec1;
I moved it up a few lines, and now it compiles fine (I'm using ModelSim in Verilog mode).

It appears to simulate fine too. It's a 24-hour BCD clock. What malfunction do you see? Which simulator are you using?

You don't need two sets of hour,min,sec signals. You could define them as output registers, and eliminate the assign statements. I did that, and also reformatted the indenting to my favorite style (so I can read it!):

hi i find some logical error in the code
in this block:

if (hour[7:4] < 4'b0010) begin
if (hour[3:0] < 4'b1001) begin
hour[3:0] <= hour[3:0] + 1;
end else begin
hour[3:0] <= 0;
hour[7:4] <= hour[7:4] + 1;
end
end else begin
if (hour[3:0] < 4'b0011) begin
hour[3:0] <= hour[3:0] + 1;
end else begin
hour[7:4] <= 0;
hour[3:0] <= 0;

if you observe closely you are checking for the condition hour[7:4]=2 and hour[3:0]=9 this makes it 29 but what we exactly want to check is for 24 what i feel you intended to do was check for 23:59 but you probably missed.

Pleasse correct me if i am wrong.

thanks

The code uses less-than tests, not equality tests.

Using ModelSim, I see it counting the hours correctly from 00 through 23, then back to 00.

thank you very much guys,i will do it again.i thank you for all of your adivce.