+ Post New Thread
Results 1 to 2 of 2
- 22nd May 2008, 20:16 #1
- Join Date
- Jun 2007
- 0 / 0
Cadence has a logical "alias" symbol that permits one to use multiple names for the same physical net. There are numerous uses of this symbol in a design I am referencing, and I would like to retain the original schematic design.
For example, a particular pin that returns current from a sensing loop is called BOOST_SENSE_N, but happens to be connected to ground via one of these alias symbols. In @ltium however, the net name is overidden with 'GND', which makes it more difficult to track when laying out the PCB. Each one also generates a compiler warning. This means I must review all the warnings, not just new ones, each time I make an edit. It slows me down, and increases the possibility of errors.
The only way I know to overcome this is to use a jumper (a zero-ohm resistor). This unfortunately invokes a physical component in the PCB layout. For obvious reasons, I am looking for a logical, rather than physical solution. I have also considered a virtual library component (two pins end-to-end for example), but it still requires manual placement and routing. A logical solution is the only way.
- 22nd May 2008, 20:16
23rd May 2008, 22:01 #2
- Join Date
- Feb 2002
- 408 / 408
Altium doesn't have an equivalent to net alias. It does allow the use of a "Net Tie" which is a two pin component with a wire between the two pins. This specially defined symbol/component lets you connect two different named nets together without creating compiler or DRC errors. You can define it as a physical or just logical component by specifying BOM or non-BOM as the type.
I generally use two short length pins back-to-back. You set the Net Tie property in the schematic symbol and/or PCB footprint properties dialog where it says "type". It's mentioned in the help document TR0111.
1 members found this post helpful.