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How to back-annotate R.L.C parasitics of IC Package to sim

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chris_li

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ic package parasitics

Hi All,

Anybody who can tell me how to back-annotate lumped R.L.C parasitics of IC pacakge to gate-level netlist for post-simulation? Commercial tools like Star-RCXT, Fire&Ice just recognize layout and extract RC data, then calculate into SDF delay file, but how to convert R.L.C data of IC packge into SDF delay file? Who can direct me how to take the impact of R.L.C parasitics of package into consideration before tapeput. Thx a lot.
 

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