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common centroid in Analog layout

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chinni_25

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common centroid in analog layout

What's meant by interdigitation in Analog layout design?
Could anyone Explain about common centroid in Analog layout?
 

analog layout matching

and 'interdigitization' is also interesting, as mehods to decrease mismatch effect on the FETs

thanks, Dan
 

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    chinni_25

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when to apply analog layout

Common Mode and Interdigitization is basically just a method of layout of devices. The basic idea is to distribute the devices so that they are more spread out across the design. It is relevant for matching of devices.

Say you are laying out a differential amp. Properly designed, main cause of mismatch would be due to layout of the input transistors. These have to be matched so that if similar inputs are fed into each, they will cancel out.

In order to make sure that processing the transistors are equivalent, the easiest way is to make sure they are either as close as possible or the two transistors are layout in a way that eats into each others space - interdigitized. So you create say a multi-finger transistor and place the transistors alternately between the two and route accordingly. This way, if process shifts at certain portions of the wafer, both transistors are affected -- hence remain matched.

Common centroid is a method of interdigitization. With this method, you consider the matching of the devices from all directions - hence typically square.

For more info, google :p :)
 

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    chinni_25

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analog layout design

moriar said:
Common Mode and Interdigitization is basically just a method of layout of devices. The basic idea is to distribute the devices so that they are more spread out across the design. It is relevant for matching of devices.

Say you are laying out a differential amp. Properly designed, main cause of mismatch would be due to layout of the input transistors. These have to be matched so that if similar inputs are fed into each, they will cancel out.

In order to make sure that processing the transistors are equivalent, the easiest way is to make sure they are either as close as possible or the two transistors are layout in a way that eats into each others space - interdigitized. So you create say a multi-finger transistor and place the transistors alternately between the two and route accordingly. This way, if process shifts at certain portions of the wafer, both transistors are affected -- hence remain matched.

Common centroid is a method of interdigitization. With this method, you consider the matching of the devices from all directions - hence typically square.

For more info, google :p :)
Click to expand...

thanks for your answer.
basically, I have idea about mismatch, how this influencing and where is the weakness in my design, but I'm nothing in layout and have to trust on 100% for layout engineer. that is why my interest...

btw, to decrease mismatch influence, someone on this forum recommend to use the as big as possible sizes of transistors ... but in my case I can increase (on the weak points - inverters) just a W, but L must be still minimal.
is any have idea, if I will use a maximal W and minimal L for my inverters, is the threshold will jump a lot ? (currently, can not apply monte carlo simulation cause the library is not reaby...)
 

To quote : " btw, to decrease mismatch influence, someone on this forum recommend to use the as big as possible sizes of transistors ... but in my case I can increase (on the weak points - inverters) just a W, but L must be still minimal.
is any have idea, if I will use a maximal W and minimal L for my inverters, is the threshold will jump a lot ? (currently, can not apply monte carlo simulation cause the library is not reaby...) "

I'm not sure how the copy and paste message thing works so I just do it manually :p

I'm going to say, no because even if you use maximal W and minimal L, you can always fold the transistors. This is getting out of topic though. If you search the forum you may find more information related to this. Cheers.
 

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