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basic question on sigma delta modulators

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svensl

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Hello all,

So I was wondering how to choose the reference voltage for the DAC in the sigma delta ADC. Considering a 1.5V process the input sinusoid is centred around 750mV. With the quantizer levels of 1.5V and 0V what value do I need to feed back to the input. If I were to use 1.5 and 0V as feedback signal, I would get negative values after subtracting the feedback from the input. So how do I avoid going below 0V?

Thanks
 

I think the high and low references which are fed back are decided by the output swing of the integrator being used. This ensures that the integrator never saturates.
 

if the feedback voltage is vrefp and vrefn, the two levels of quantizer are +/-(vrefp-vrefn), the full scale is 2*(vrefp-vrefn). if you set proper integrator gain, it will havn't negative voltage in output of integrator.
 

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