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range must be bounded by constant expression in verilog?

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gvm0072002

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range must be bounded by constant expressions

for(i=0;i<56;i=i+8)
begin

if (string[i+7:i]<="G")
y[i+7:i]<="C";

ijust want to know what is wrong in the above statement, it is showing an error of
range must be bounded by constant expression(verilog).
 

verilog range

Here you must have declared
string as reg [56*8:1] string;
And verilog standard says that you can not assign variable part select of a vector;
that means string[i+7:i] is not allowed if i is not a constant.
parameter i = 10; string [i+7:i] = 'A'; is allowed and valid.
In ur case what you can do is declare string as array of chracters
Code: 
reg [8:1] y_array [0:55];
reg [8:1] string_array [0:55]; //56 character array 
wire [56*8:1] string, y;
for (i=0; i<56; i=i+1) begin
    if (string_array[i] <= 'G')   
      y_array[i] <= 'C'; 
end
assign string = {string_array[55], ........, string_array[0]};
assign y = {y_array[55], ......., y_array[0]};

Hope this helps!

Hope this helps!
 

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