ASIC_intl
Banned
design compiler report_timing
Hi
I have a design. I am using the Design compiler for synthesis. I know my design is a single clock design.
How can I see the slack value for the critical path in my design.
Do I need to create a path group consisting of all the d-inputs of the d-flops in my desogn for doing that while using report_timing command?
Thank
ASIC
Hi
I have a design. I am using the Design compiler for synthesis. I know my design is a single clock design.
How can I see the slack value for the critical path in my design.
Do I need to create a path group consisting of all the d-inputs of the d-flops in my desogn for doing that while using report_timing command?
Thank
ASIC