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Specifications for top level clock tree synthesis

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alchemist1

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Hi,

Suppose we are assigned to do cts on a design. What are the specifications we can except from the top level and how do we achieve it specifically other than following normal options.


thankz
 

Clock tree synthesis

You should expect/need the following:

1) clock skew
2) clock slew
3) insertion delay requirements
4) source latencies
5) case analysis in the SDC
6) buffer/inverter types
7) skew groups...if necessary

Added after 52 seconds:

also,
8) nondefault routing rules for clocks
9) shielding...if necessary
 

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