tromeros
Member level 1
Hello everyone.
I’m trying to design a cmos distributed differential VCO for a project, which means 2 parallel microstrip lines for the drain load and another 2 microstrip lines for the gate line.
For the inverter i’m using the “delay variation by positive feedback” tuning technique, proposed by Behzad Razavi in his book “Design of analog cmos integrated circuits”.
I’m trying, based on a tsmc 90nm process available to me by the electronics laboratory at my school, to implement this distributed circuit.
The problem is that I don’t seem to understand how to implement the parallel transmission lines, because there are 9 metal layers available to me and i’m trying to achieve a 50 ohm resistance at 10GHz.
The main quastion I have is what metal layer to use as a ground reference. Should I use metal1 of the process?
However, in that case there is a maximun in the width of the metal.
I am a newbie to this area so any ideas about the line would be much appreciated!
Thank you in advance.
I’m trying to design a cmos distributed differential VCO for a project, which means 2 parallel microstrip lines for the drain load and another 2 microstrip lines for the gate line.
For the inverter i’m using the “delay variation by positive feedback” tuning technique, proposed by Behzad Razavi in his book “Design of analog cmos integrated circuits”.
I’m trying, based on a tsmc 90nm process available to me by the electronics laboratory at my school, to implement this distributed circuit.
The problem is that I don’t seem to understand how to implement the parallel transmission lines, because there are 9 metal layers available to me and i’m trying to achieve a 50 ohm resistance at 10GHz.
The main quastion I have is what metal layer to use as a ground reference. Should I use metal1 of the process?
However, in that case there is a maximun in the width of the metal.
I am a newbie to this area so any ideas about the line would be much appreciated!
Thank you in advance.
