Antenna Violation in the case of Std cell design

Can anyone tell me how to solve the antenna violation in the case of standard cell?

Bcz here we use only one metal layer that is M1 so there is no chance of jogging or layer hopping....So do we have to use antenna diodes? here If yes then how to place and for doing this do we have to make another standard cell called as antenna diode and instantiate wherever we hv any antenna violation??????????

Reply me...

There's no need to create an "antenna diode" cell if you do not want to create it...

If you have a P-substrate process, a simple N+ contact placed over substrate with the metal connected to the line with "antenna violation" will act as antenna diode as described in other posts.

We can't use layer hopping technique or jogging techniques right?

Jogging and layer hopping are same????

From what you mention about having only one metal then you're right, you can't jump into a M2 to avoid the antenna violation.

Regarding your final question, I did hear both names for the technique I've just described above, so my answer would be YES...

Normally we won't consider Antenna Violation for std cells as it will lead to area increase.. So, we normally go for placing the Antenna diode or Metal Jogging at the SOC level.

Additional comment... as mentioned by kumar, as rule of thumb we use not to put antenna diodes (or do metal jogging) at std. cell level and, in addition, at block level, we do not use to do the same at any net that is connected to block's I/O pins, since that net, at higher level, could be going to a diffusion that give us our needed "discharge path"...

Layout master could u please explain me once again i did not understand about ur block concept.....Why it not happens in full chip then??

" we do not use to do the same at any net that is connected to block's I/O pins, since that net, at higher level, could be going to a diffusion that give us our needed "discharge path"...

I meant, when you work at lower hierarchy level (blocks that together create the toplevel or chip...).

Usually you'll check antenna directly at toplevel, then you'll see the complete picture but sometimes you might test it at lower hierarchy (a block). There is when I say you might wait for a toplevel check to see if REALLY you have a violation...

Was it clear now?

yes thnks

Added after 1 minutes:

Please explain the difference between Jogging and Layer hopping

same thing

Thanks alot Layoutmaster.. Very good explanation...

I was told that there is a slight difference between jogging and Layer hopping...may i knw wts tht ?

And one more point is...why do we go for upper layers when we do layer hopping why not we go for lower layers??

->why we go for upper layer for layer hopping is because during fabricatin masking is going low layer to top layer,antinna violation is main b'use of charge deposition on long nets if u go for lower layers charge will be continue flow b'use lower layer already there,if u go for upper layer change will be dischaged when upper layer layed.

Let's clarify something... when dealing with antenna effect there are not much layers involved, just POLY, M1 and (if you process have) M2 (or top, depends on your process naming convention...)

The charge you might have trapped when processing POLY mask should be having a discharge path as soon as you process M1 (by connecting that poly with a diffusion that could be a transistor drain, or whatever, or an antenna diode).

When you process the M1, additional charges will be present to the already caused by POLY stage (if a discharge path is not present). There is when you do (with a shortest M1 as possible) a layer hopping in order to minimize the additional charges accumulation. In other words, an as I stated in other posts, this will allow you to avoid getting a violation error when checking (since the check is based on area ratios) but, as you can see, this is only a partial solution... but this answers why you do an upper layer hop.