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Design and Analysis of VCO in PLL System

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khouly

khouly

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PLL design

i am designing a integrated PLL , the VCO is fully integrated with inversion mode PMOS varactor with provide KVCO is negative the frequency decrease as increase in controll voltage

the system analysis , KVCO in positive , so
i am thinking to invert the inputs of the phase frequncey detector

make the ouput of the divider insted of the reffernce oscillator and put the reffernce osillator insted of the ouput of the divider

is this right or just connect the loop.
 

Re: PLL design

There is nothing sacred about which inputs to the phase detector are the reference and VCO divided signal. You can always put whatever dividers you want in both the VCO and reference paths. Some commercial chips have dividers in both lines that you can program the divide by N values.
 

Re: PLL design

Hi.
I think that your design is incorrect and your PLL loop will be unstable.
Best regards.
 

Re: PLL design

thanks

the KVCO is negative and in system design , it is positive

how to make the PLL stable ,
may i put KVCO in the system analysis negative or what to do
 

Re: PLL design

u can do that in three ways:
1.use a negative gain in forward path, after PFP-CP. usually it is combined with RC filter to produce an active filter with a minus sign. for using it be careul, since it make extra phase noise of PLL due to OPAMP noise.
2.Replace up(UP) and down(DN) signals with each other and apply them to CP and filter. in this way a logical minus is produced in the loop without any pahse noise increase.
3.Replace inputs signals to PFD with each other. this is like second solution.

for meaningful design and scematic the best idea is second one!

BEST!
 

Re: PLL design

many thanks

this what i was thinking ,
but , i have just simulated the PLL in time domain using MATLAB without any modification , and it locked and produced the output

is there any reasone for this
 

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