hi
i have simulated and then synthesised a verilog code for both 8-bit & 16-bit array multiplier using carry sav adders on Xilinx.8.2. the results i got are as follows.
result for 16- bit array multiplication
Minimum period: 19.961ns (Maximum Frequency: 50.098MHz)
Minimum input arrival time before clock: 2.443ns
Maximum output required time after clock: 20.110ns
Maximum combinational path delay: No path found

result for 8-bit array multiplication
Minimum period: 21.003ns (Maximum Frequency: 47.612MHz)
Minimum input arrival time before clock: 2.447ns
Maximum output required time after clock: 22.777ns
Maximum combinational path delay: No path found

I found this result very strange, because as the number of bits are increasing the delay of multiplier should increase as per my knowledge. I have also checked the complete outputs for both and both are working correctly.
Can anybody tell me the significance of the timimng report i got in Xilinx.
Is minimum period equal to delay of the multiplier??????????

Plz help me out.......