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Urgent help needed about Layout!!

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berko3000

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Hi guys,
I have a problem with the simulation of my full adder cell layout. I drawed its layout in Magic but when I try to simulate it using Hspice and Awanwaves I'm getting spikes which I circled in red in this link:

Code: 
**broken link removed**

How can I fix it?

thanks
 

The glitches (spikes) will be due to transition times from 0~1 and 1~0 in your design.

It is not possible to get from a low logic state to a high logic state without some time passing. As seen in the waveforms at the bottom of the picture, the transitions take time.

Transition can be set to a minimum in some simulation software to provide nice-looking simulation graphs but does not reflect what really happens. Capacitance can be the cause.

I think additional logic can be added to remove the glitches.
 

so which capacitance should I check ? The load capacitance at the output of the sum signal?
 

I'm not totally sure (as I've only had an introduction to some bits of VLSI) but parasitic capacitance depends on the technique used to develop the circuit and its silicon layout.
 

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