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Can digital correction tolerate the settling error of MDAC?

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for a 1.5 bit per stage pipelined adc, due to digital correction,the comparator can tolerate offset voltage of +-vref/4,what i want to ask is that in the offset range of +-vref/4,if the settling accuracy of MDAC is not enough,i.e. for 10 bit resolution and full range of 1V,the settling error is larger or smaller about 1mv,that is,for output of 200mv,the actual value is about 199mv,not in the range of 198.8mv~200.2mv,is that ok?
can digital correction tolerate the settling error of MDAC?
pls give me some advice.
thanks all .
 

about pipelined adc

any advice?
for 10 bit resolution,what extent of error caused by residue amp can be tolerated?
and what's the tolerated range of vin?
 

about pipelined adc

settling error must be smaller than half LSB
 

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