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digital pick calcultion

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shadeslayer

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hi all

i wrote the following code ,, can anybody tell me if thr is anything missing?

Code:
-----------------------------------
-----------------------------------
---  digital pick amp calc --------
-----------------------------------
-----------------------------------

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library ieee;



entity sat is 

port( 
	DIN: in srd_logic_vector(7 downto 0);     ----   data input lines
	DOUT: out std_logic-vector(7 downto 0);   ----   data output line
	reset: in std_logic;                      ----   reset signal
        nochange: in std_logic;                   ----   to indicate the no data change done
     );

end sat;


architecture behavioral of sat is 
type rega is array (0 to 7) bit;          --------- RegA= refrance initialy 0
type regb is array (0 to 7) bit;          --------- RegB= data taken from user 

begin

   process(one)
    variable reg1:rega;
    variable reg2:regb;

   
    begin

        procedure transfer is
         
          begin
            
            reg1(0)<=reg2(0);       ---------------- subroutine for data change
            reg1(1)<=reg2(1);
            reg1(2)<=reg2(2);
            reg1(3)<=reg2(3);
            reg1(4)<=reg2(4);
            reg1(5)<=reg2(5);
            reg1(6)<=reg2(6);
            reg1(7)<=reg2(7);

          end procedure transfer;

     
     DIN(0)=>reg2(0);               --------------
     DIN(1)=>reg2(1);               --------
     DIN(2)=>reg2(2);               -----
     DIN(3)=>reg2(3);               -- Data teken into RegB 
     DIN(4)=>reg2(4);               --
     DIN(5)=>reg2(5);               -----
     DIN(6)=>reg2(6);               --------
     DIN(7)=>reg2(7);               --------------


     reg1(0):=0;                    --------------              
     reg1(1):=0;                    --------
     reg1(2):=0;                    -----
     reg1(3):=0;                    -- RegA is initialized to zero
     reg1(4):=0; 		    --
     reg1(5):=0;                    -----
     reg1(6):=0;                    --------
     reg1(7):=0;                    --------------


       if(reg2(0)>reg1(0))then              ---------------------------------
	  transfer;
  
       elseif(reg2(1)>reg1(1))then          -----------------------------
	  transfer;
  
       elseif(reg2(2)>reg1(2))then          -------------------------
	  transfer;
  
       elseif(reg2(3)>reg1(3))then          -----------------  transfer data if RegB > RegA 
	  transfer;                                          
  
       elseif(reg2(4)>reg1(4))then          ----------------- thus at end we get maximum value
	  transfer;
  
       elseif(reg2(5)>reg1(5))then          -------------------------
	  transfer;
  
       elseif(reg2(6)>reg1(6))then          -----------------------------
	  transfer;
  
       elseif(reg2(7)>reg1(7))then          ---------------------------------
	  transfer;
       
       else
          nochange;=1;                       ----indicate no change (not required)
  
       end if;

     
     reg1(0)=>DOUT(0);                   ----------- data taken out
     reg1(1)=>DOUT(1);
     reg1(2)=>DOUT(2);
     reg1(3)=>DOUT(3);
     reg1(4)=>DOUT(4);
     reg1(5)=>DOUT(5);
     reg1(6)=>DOUT(6);
     reg1(7)=>DOUT(7);     

    end process;

end behavioral;
[/code]
 

1. nochange must be out
2. you must use <= in nochange association
3. you did not define signal named one (in the process sensitivety list)
4. you have a syntax mistake in din declaration (srd_logic...)

Added after 7 minutes:

And several others
 
plz tell me which others??

i dont want to any change in date if any conditions is not setisfied ,,it will b okie if i dnt use nochange signal but instade wht shuld i use?
 

Well, I do not have time to explain, but you don't define the procedure correctly, and don't call it correctly. But I cannot correct you, because I cannot get what you are exactly doing. Did you develope any algorithm? Which software tool do you use?

Added after 7 minutes:

I could recommend you some useful books, like:
RTL Hardware Design Using VHDL by Pong P. Chu,
Circuit Design with VHDL by V. A. Pedroni,
Design Recipes for FPGAs by P. Wilson, etc.
 
Here I did an example:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity d_p is
Port ( din : in STD_LOGIC_VECTOR (7 downto 0);
dout : out STD_LOGIC_VECTOR (7 downto 0);
reset : in STD_LOGIC);
end d_p;

architecture Behavioral of d_p is

begin
process (din, reset)
variable dat: std_logic_vector(7 downto 0) ;
begin
if (reset='1') then dat:="00000000";
elsif din>dat then dat:=din;
end if;
dout<=dat;
end process;
end Behavioral;

Added after 8 minutes:

Here is the simulation:
 
oh its nice ,,,, thx ,,,

i use xilinx9.2i and activehdl7.1

Added after 2 minutes:

i further want to add ,, refrence ,and counter ,,,

ie ,,, if i take 03 as refrence thn i will chk how many time i got data above 03 and if i get data countinuously 03 for 1 min thn i want to stop the process ,,,

i thought of using protmaping ,,and combine components ,,, but i m not sure how to add this in this code,,,
 

For counter you can use Language Templates from inside ISE (menu Edit).
For reference value you can use generic command.
To combine components you have to use structure description. It's good to examine the "ISE In-Depth Tutorial" as well as ISE Quick Start Tutorial.
You can find them inside :
...Xilinx\doc\usenglish\books\docs
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity d_p is
Port ( din : in STD_LOGIC_VECTOR (7 downto 0);
ref : in STD_LOGIC_VECTOR (7 downto 0);
dout : out STD_LOGIC_VECTOR (7 downto 0);
h_out: out STD_LOGIC_VECTOR (3 downto 0);
reset : in STD_LOGIC);
end d_p;

architecture Behavioral of d_p is
begin
process (din, reset)
variable dat: std_logic_vector(7 downto 0);
variable cnt: integer;
begin
if (reset='1') then
dat:=ref;
cnt:=0;
elsif din>dat then
dat:=din;
cnt := cnt+1;
end if;
dout<=dat;
h_out<= CONV_STD_LOGIC_VECTOR(cnt,4);
end process;
end Behavioral;
 
i didnt got this code ?? confused ,,,,,

let i explain in detail what to b done ,,, thn i think u will understand clearly what i m trying to make ,,,

i m using 2 comparators ,, one will calculate the pick value or u can say maximum value ,, another will give pule whenever my input is greater thn ref say 03 ,, now
if my input dontgo above 03 for 2mins or 3mins then my whole process will stop ,,,

hope u got it ,,, i will try to upload a block diagram,,

btw thx for this code if u tell me litel bit abt this code ,,

Added after 3 minutes:

i also thout to use counter so that i will come to know how many times my input goes above the refrence voltage
 

Hi,
I attached the symbol.
When reset=1 then h_out=0.
The first values of d_out is the reference value.
Every time d_in becomes greater than current value of d_out, then d_out=d_in.
Every time d_out changes its value, h_out increases by 1 (it counts how many times d_in had been greater than d_out).
 
Now I saw, you meant h_out must count how many times the input is greater than reference value, so a little change of the code sould be done.
 
yes and also the reset signal shuld b 1 ie all process shuld stop when din is below ref for 2or 3 min ,,, and the 1st code u gave shuld also b thr ,,,

so at the end of process i shuld get the pick value at the output countinuously ,,,
 

How will you receive 2 or 3 min. period? I mean, do you intend to synthesize it or not? If you will not synthesize the code, you can use "after", else must have some reference clock signal end realize another counter to divide the clock frequency.
 
what ??? i dint got u ,, what u r trying to say?

Added after 7 minutes:

i mean to say that with the help of one comparator ,, i will be geting pick value,,,

and with the help of another comparator i can get howmany time my signal goes above my refrance voltage ,,,

see i wll give a damping wavefor as a input to the ADC ,,and the digital output i will use for simulation ,,ryt,,,


now if i m having a daping waveform at the input thn after some time my signal will reach a steady state ,,, so after that i dont have need to check for pick amplitude ,,,

so what i thought is if i dont get signal above my ref voltage for 2or 3 mins then i shuld reset my system ,, and will store the my pick value somewher frm where i can get it at the output,,,,

inthe 1st program u gave it will b chaknig for pick values and its woriknig good ,,, but as i musing damping wave(acostic emission signal) as input thn after some thim signal will b steady ,, so that will b end of one event ,,, thn again after some time i will get another damping signal , ,which will also b a damping signal this is my second event ...

hope u understood
 

What do you mean with "2 or 3 min." I think you mean minutes. So, in VHDL you don't have the possibility to measure time, except if have a reference frequency and you count its cycles. That is why you will nead a counter. Or, you have to find another way to find the steade state (say, if the number of times the input leaves under its pick level; but do not forget there could be some picks above and under the steade state).
 
yes i m talknig about miutes ,,, it will b better to use the conter which genrated puleses after ever few secnods and by conting tm we can do tht ,, but i m not abel to code that ,,, cant we use the delay that is wait for some time type statements ???

please write the code according to what u got ,, i think u got full thing what i want to say ,, as u explaind me abt how we can use conter to get 2 or 3 minuts chkout ,,,

thx
 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity d_p is
Port ( din : in STD_LOGIC_VECTOR (7 downto 0);
ref : in STD_LOGIC_VECTOR (7 downto 0);
reset : in STD_LOGIC;
changed : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR (7 downto 0));
end d_p;

architecture Behavioral of d_p is
begin
process (din, reset)
variable dat: std_logic_vector(7 downto 0);
begin
if (reset='1') then dat:=ref;
elsif din>dat then dat:=din; changed <= '1';
else changed <= '0';
end if;
dout<=dat;
end process;
end Behavioral;




library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity timer is
Port ( reset: in STD_LOGIC;
clk: in STD_LOGIC;
steady: out STD_LOGIC);
end timer;

architecture Behavioral of timer is
begin
process (clk, reset)
variable cnt: integer :=0;
variable ended: STD_LOGIC;
constant t_per: integer :=12;--2min if clk=0.1Hz (10 sec)
begin
if reset='1' then cnt:=0; ended:='0';
elsif (clk'event and clk='1' and ended='0') then cnt := cnt+1;
end if;
if cnt >= t_per then cnt:=0; ended:='1';
end if;
steady <= ended;
end process;
end Behavioral;





use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pick_det is
port ( clock : in std_logic;
din : in std_logic_vector (7 downto 0);
ref : in std_logic_vector (7 downto 0);
reset : in std_logic;
pick_value : out std_logic_vector (7 downto 0);
ready : out std_logic);
end pick_det;


architecture BEHAVIORAL of pick_det is
signal rst : std_logic;
component d_p
port ( reset : in std_logic;
din : in std_logic_vector (7 downto 0);
ref : in std_logic_vector (7 downto 0);
changed : out std_logic;
dout : out std_logic_vector (7 downto 0));
end component;

component timer
port ( reset : in std_logic;
clk : in std_logic;
steady : out std_logic);
end component;

begin
U1 : d_p
port map (din(7 downto 0)=>din(7 downto 0),
ref(7 downto 0)=>ref(7 downto 0),
reset=>reset,
changed=>rst,
dout(7 downto 0)=>pick_value(7 downto 0));

U2 : timer
port map (clk=>clock,
reset=>rst,
steady=>ready);

end BEHAVIORAL;
 
can u give bit explanation what is hapening ,,, be-cause waveforms are not clear,,, i mean valus i can abel to see properly,,, thx

Added after 19 minutes:

and cpuner shuld count how many time input is greator then ref signal not how many times my pick value changes ,, i think in this program its showing how many times it is cchanging ,,,


in my code which i gave at starting i used nochang signal just coz at tht time i didnt rememberd null statement ,, but that nochange is not req ,,, counter will tell me howmany pulses i got above ref signal ,,,


in the calulation of acostic signals this helps lot in clulating material strength,,,
 

When (reset=1) then dout=ref.value.
When (reset=0 and din>dout) then dout=din, the timer starts to count from the beggining (0), clearing the output (signal) steady.
When reset=0 and din<dout then timer increases its contents on each rising edge of clock pulse. When it reaches its end state (12 it his case) it resets itself and sets the signal steady.
The circuit is a structural code. The first entity declaration (pick_det) is the whole device. In architecture the first component (d_p) is the comparator, the second - the timer. U1 and U2 are instantiations of the components.
I will do some changes to count how many times the input is higher than the reference value.
 
yes we need to count how many times the input is higher then the ref value ,,, here i m writing the good explanation tht i can give ,,,

when reset=1 then system shuld stop or not work

now whn reset =1 thn

dout=pick value of din(loop will work same as ur 1st code)

if dint> ref thn it shuld increase count
and if din<ref for say 12 clk pules thn reset=1 and sys will stop,,,,

now to again start sys to work we shuld manualy make reset =0

i think this is bit clear,,,
 

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