shadeslayer
Member level 2
hi all
i wrote the following code ,, can anybody tell me if thr is anything missing?
[/code]
i wrote the following code ,, can anybody tell me if thr is anything missing?
Code:
-----------------------------------
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--- digital pick amp calc --------
-----------------------------------
-----------------------------------
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library ieee;
entity sat is
port(
DIN: in srd_logic_vector(7 downto 0); ---- data input lines
DOUT: out std_logic-vector(7 downto 0); ---- data output line
reset: in std_logic; ---- reset signal
nochange: in std_logic; ---- to indicate the no data change done
);
end sat;
architecture behavioral of sat is
type rega is array (0 to 7) bit; --------- RegA= refrance initialy 0
type regb is array (0 to 7) bit; --------- RegB= data taken from user
begin
process(one)
variable reg1:rega;
variable reg2:regb;
begin
procedure transfer is
begin
reg1(0)<=reg2(0); ---------------- subroutine for data change
reg1(1)<=reg2(1);
reg1(2)<=reg2(2);
reg1(3)<=reg2(3);
reg1(4)<=reg2(4);
reg1(5)<=reg2(5);
reg1(6)<=reg2(6);
reg1(7)<=reg2(7);
end procedure transfer;
DIN(0)=>reg2(0); --------------
DIN(1)=>reg2(1); --------
DIN(2)=>reg2(2); -----
DIN(3)=>reg2(3); -- Data teken into RegB
DIN(4)=>reg2(4); --
DIN(5)=>reg2(5); -----
DIN(6)=>reg2(6); --------
DIN(7)=>reg2(7); --------------
reg1(0):=0; --------------
reg1(1):=0; --------
reg1(2):=0; -----
reg1(3):=0; -- RegA is initialized to zero
reg1(4):=0; --
reg1(5):=0; -----
reg1(6):=0; --------
reg1(7):=0; --------------
if(reg2(0)>reg1(0))then ---------------------------------
transfer;
elseif(reg2(1)>reg1(1))then -----------------------------
transfer;
elseif(reg2(2)>reg1(2))then -------------------------
transfer;
elseif(reg2(3)>reg1(3))then ----------------- transfer data if RegB > RegA
transfer;
elseif(reg2(4)>reg1(4))then ----------------- thus at end we get maximum value
transfer;
elseif(reg2(5)>reg1(5))then -------------------------
transfer;
elseif(reg2(6)>reg1(6))then -----------------------------
transfer;
elseif(reg2(7)>reg1(7))then ---------------------------------
transfer;
else
nochange;=1; ----indicate no change (not required)
end if;
reg1(0)=>DOUT(0); ----------- data taken out
reg1(1)=>DOUT(1);
reg1(2)=>DOUT(2);
reg1(3)=>DOUT(3);
reg1(4)=>DOUT(4);
reg1(5)=>DOUT(5);
reg1(6)=>DOUT(6);
reg1(7)=>DOUT(7);
end process;
end behavioral;