atena
Full Member level 1
I have a few question :
(1) I need a complete library pack including technology library ( for optimization ) , link library, symbolic library and especially a verilog or VHDL code to describe the library's elements. The technical library must contain both timming model as well as SDPD for power modelling ( Leakage and Internal ) .... If anyone can have me plz send me those libraries thru my email adress : andrew_nguyen85@yahoo.com
In the begining time i have tried to make my own library but it was too complex and involving too many others analog design tools.Thanks very very much if anyone can have me to resolve this problem. I'm stucking with it for nearly one month.
(2) In Design Compiler, when translating the design from BEHAVIORAL model to Gate-level model using the instruction : write -format [vhdl|verilog] -output filename
is there any precaution in compiling step regarding map and area effort ?
I have translated the below ready_made code to gate-level using core_typ.db library but my translation result failure when i fetched it to PrimeTime. PT_SHELL show that there are many errors in finding the submodule elements.
(3) Which tool in SYNOPSYS (or CADENCE) is used to convert from (top-down) Behavioral HDL-A and HDL-AMS design file to Spice (bottom up) file ?
(1) I need a complete library pack including technology library ( for optimization ) , link library, symbolic library and especially a verilog or VHDL code to describe the library's elements. The technical library must contain both timming model as well as SDPD for power modelling ( Leakage and Internal ) .... If anyone can have me plz send me those libraries thru my email adress : andrew_nguyen85@yahoo.com
In the begining time i have tried to make my own library but it was too complex and involving too many others analog design tools.Thanks very very much if anyone can have me to resolve this problem. I'm stucking with it for nearly one month.
(2) In Design Compiler, when translating the design from BEHAVIORAL model to Gate-level model using the instruction : write -format [vhdl|verilog] -output filename
is there any precaution in compiling step regarding map and area effort ?
I have translated the below ready_made code to gate-level using core_typ.db library but my translation result failure when i fetched it to PrimeTime. PT_SHELL show that there are many errors in finding the submodule elements.
(3) Which tool in SYNOPSYS (or CADENCE) is used to convert from (top-down) Behavioral HDL-A and HDL-AMS design file to Spice (bottom up) file ?