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Synthesizable adder in Verilog language

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andrew257

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hi all,

is it possible to use the "+" in verilog language and expect the compiler to make the logic for an adder.

e.g

input a;
input b;
output c;

assign c = a + b;

is code like this synthesizable or would i actually have to look at making an adder from logic gates etc.

thanks
 

sythesizable adder

Yes, that's a reasonable expectation. Modern FPGA/CPLD HDL compilers do a very good job synthesizing the '+' operator.
 

Re: sythesizable adder

hi echo, thanks for the reply,

what about adding signed numbers. i know there is a signed statement in verilog that can be used but is it synthesizable?

basically i need to add two sets of numbers together. both are 8 bits. however i first need to convert the bits to twos compliment form and then add them together.

this is an attempt to mix two analogue signals together in the digital domain rather than use a analogue circuit to mix the signals. If anyone has any ideas how best to tackle this that would be great.

thanks
 

sythesizable adder

Verilog supports signed arithmetic. Simply declare your signals as 'wire signed' or 'reg signed' or 'output signed' or whatever.

Where are your two sets of numbers? Stored in an FPGA RAM? Arriving a byte at a time from an external device? Something else?
 

Re: sythesizable adder

My normal way would be to start a FPGA tool (I use Altera Quartus) and try some code.

Conversion from offset binary to two's complement is by simply inverting the most significant bit, e. g. XOR x"80" for a 8-bit number in VHDL.
 

Re: sythesizable adder

Yeah FvM you are correct i am using offset binary, i forgot to mension that in an earlier post.

the data is coming on a databus, all 8 bits at a time. stored in a reg and then added together.

if i declar the reg as signed will it automaticaly change the MSB for me i.e convert offset binary into signed?

ive wrote some code and it simulates fine, however how do i know the signed part is functioning?

in the simulator i can chose to view it as binary, hex, signed and unsigned.

how can i see if its actually converting the data into signed? or am i missing something here.
 

Re: sythesizable adder

You should play around with numerical examples, then you see if the signal is converted correct. Anyway you have to invert the LSB to get 2s complement from offset binary. For an adder, there is actually no difference between signed and unsigned representation, the bit operation is identical.
 

sythesizable adder

Verilog doesn't know anything about offset-binary format, so it won't automatically do the offset-binary-to-signed conversion for you. You need to invert the MSB yourself. (I'm sure FvM meant MSB instead of LSB.)

I think you are trying too hard to find differences between signed and unsigned processing. The two are almost identical, except for sign extension (when widening a signed value, you need to replicate its sign bit).

Since your data arrives one-byte-at-a-time, you can use an accumulator to compute the sum: y <= y + data. To avoid overflow, the accumulator 'y' should of course be wider than 'data'. Since 'data' is signed, 'y' should also be signed, so Verilog will automatically do the sign extension.
 

sythesizable adder

I have a (+) operator in my RTL that's supposed to infer an adder .. the problem is with the size of input operands versus the sum size ..
Ideally, a signed (or even unsigned) adder should have an output size = size of one of the inputs +1 .. in other words, my adder adds two 32-bit signed numbers .. hence, the output should be 33-bits ..
The synthesis tool gives me an error on that as it see the RHS size not equal to the LHS size!! ..
When I change the sum size to to 32bits, it works !!

How then it will be able to handle the carry out ?
 

Re: sythesizable adder

One or both summands have to be resized to 33 bits.
 

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