help decoding VHDL/AHDL code

ahdl code

Can someone help me understand what this code is doing. I was tasked with modifying the adress length from 32 bits to 31 bits, to 30 bits......and watch what happens.


subdesign adr_tstr


--Connections active HIGH
(
clock :input; -- timebase input
run :input; -- runs and resets the address decoder
radio_rx :input; -- radio receive serial line
rad_clk :input; -- clock from the radio
fram_err utput; -- if frame error after address match
rx_dat[7..0] utput; -- strobed 8bit data after address good
rx_strob utput; -- active hi when rx_dat[] is valid
adr_inpt[31..0] :input; -- 4 byte address field
adr_match utput; -- input stream has matched the input address field
bit_count[3..0] utput;
--chng, mark utput; -- used to indicate a change(1 to 0 or 0 to 1) serial rx
--rad_clk1 utput;
)
variable
rad_clk1 : dff; -- registered radio clock
rad_clk2 : dff; -- used to check for polarity change in clock
radio_rx1 : dff; -- registered data line
radio_rx2 : dff; -- used to check for polarity change in data
chng : dff; -- receive serial change of polarity
frm_shrt : dff; -- clock transition was too short
frm_lng : dff; -- clock transition was too long
fram_err : dff; -- either frame error
fram_tst[7..0] : dff; -- timer for bit frame testing
shift_reg[31..0] : dff; -- compares input serial stream with address
adr_match : dff; -- the shift register data has matched the address inputs
rx_strob : dff; -- 8 bits of shift register data has been put on rx_dat port
bit_count[3..0] : dff; -- bit count increments on valid input receive bit(mark)
mark : dff; -- this is the point where data is read into the shift register
rund : dff; -- registered run

begin


radio_rx1.clk = clock;
radio_rx2.clk = clock;
radio_rx1=radio_rx; -- registered receive line
radio_rx2=radio_rx1; -- one clock later, test for change in polarity

rad_clk1.clk = clock;
rad_clk2.clk = clock;
rad_clk1 = rad_clk;
rad_clk2 = rad_clk1;

chng.clk = clock;

if rad_clk1 != rad_clk2 and run then
chng = vcc;
else
chng = gnd;
end if;

fram_tst[].clk = clock;
frm_shrt.clk = clock;

if chng then
--if fram_tst[] < 20 then
if fram_tst[] < 10 then
frm_shrt = vcc;
fram_tst[] = 0;
else
frm_shrt = gnd;
fram_tst[] = 0;
end if;
else
if fram_tst[]== 63 then
frm_shrt = gnd;
fram_tst[] = 63;
else
frm_shrt = gnd;
fram_tst[]=fram_tst[] + 1;
end if;
end if;

frm_lng.clk = clock;

--if fram_tst[] > 45 then
if fram_tst[] > 60 then
frm_lng=vcc;
else
frm_lng=gnd;
end if;

fram_err.clk = clock;
if (frm_lng or frm_shrt) and adr_match then
fram_err = vcc;
else
if adr_match then
fram_err = fram_err;
else
fram_err = gnd;
end if;
end if;

mark.clk = clock;

if fram_tst[]==2 and rad_clk2 then -- get data at clock high
mark=vcc;
else
mark=gnd;
end if;

rund.clk=clock;
rund=run;
adr_match.clk = clock;

if shift_reg[31..0] == adr_inpt[31..0] and rund then
adr_match = vcc; -- address == to zero is not valid
else
if rund then
adr_match = adr_match;
else
adr_match = gnd;
end if;
end if;

shift_reg[].clk = clock;

if frm_shrt or frm_lng or !rund then -- changed !run to !rund 6/2/04 DRH
shift_reg[]=0;
else
if mark then
shift_reg31 = shift_reg30;
shift_reg30 = shift_reg29;
shift_reg29 = shift_reg28;
shift_reg28 = shift_reg27;
shift_reg27 = shift_reg26;
shift_reg26 = shift_reg25;
shift_reg25 = shift_reg24;
shift_reg24 = shift_reg23;
shift_reg23 = shift_reg22;
shift_reg22 = shift_reg21;
shift_reg21 = shift_reg20;
shift_reg20 = shift_reg19;
shift_reg19 = shift_reg18;
shift_reg18 = shift_reg17;
shift_reg17 = shift_reg16;
shift_reg16 = shift_reg15;
shift_reg15 = shift_reg14;
shift_reg14 = shift_reg13;
shift_reg13 = shift_reg12;
shift_reg12 = shift_reg11;
shift_reg11 = shift_reg10;
shift_reg10 = shift_reg9;
shift_reg9 = shift_reg8;
shift_reg8 = shift_reg7;
shift_reg7 = shift_reg6;
shift_reg6 = shift_reg5;
shift_reg5 = shift_reg4;
shift_reg4 = shift_reg3;
shift_reg3 = shift_reg2;
shift_reg2 = shift_reg1;
shift_reg1 = shift_reg0;
shift_reg0 = radio_rx2;
else
shift_reg[]=shift_reg[];
end if;
end if;


rx_strob.clk = clock;
bit_count[].clk = clock;

if adr_match then
if bit_count[] > 7 then
rx_dat[] = shift_reg[7..0];
rx_strob=vcc;
bit_count[]=0;
else
rx_dat[]=rx_dat[];
rx_strob=gnd;
if mark then
bit_count[] = bit_count[]+1;
else
bit_count[] = bit_count[];
end if;
end if;
else
rx_dat[] = 0;
rx_strob = gnd;
bit_count[] =0;
end if;

end;