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Be sure that the power supply is on before applying input to the IC.
Take care when there are several power sources in your pcb.
And as said previously, verify that the input voltage level is under the power voltage level of the IC.
Latch up in CMOS technology is caused by parasitic BJTs created between Source/Drain diffusion in adjacent n and p doped substrates needed to form the wells where are the MOSFETs. Under some circumstances (high voltages applied to the MOSFET terminals) parasitic currents made by holes and electrons flowing from a nMOS Source/Drain to adjacent pMOS Source/Drain (the base junction of the parasitic BJTs) could be strong enough to set in the conduction state these transistors which, due to the unpredictable topology, could combine in a positive feedback current loop that once activated causes a rapid increase of the current in the BJTs causing an increased power consumption of the chip or even a breakdown with a permanent damage of the circuit.
Due to the fact that the sparkle that starts the fire is the presence of high voltages the more sensitive part of IC are the I/O and power supply circuitries, therefore it is important to assure protection from over voltages to the pins connected to this part of the chip.
Latch up could be induced also by ionizing radiation, which could generate free charges in the chip due to collision with high energy particles in a avalanche style.
A manufacturing technique robust to latchup is SOI (Silicon On Insulator) process, where the n and p wells for the MOSFETs are isolated to reduce the parasitic currents but this is a very expensive process.
In normal manufacturing processes latch up risk could be reduced following some design rules, like assuring minimum spacings between n and p wells, or adding dummy collectors or guard-ring diffusions, which are highly doped zone between or around the n and p wells, used to capture the free charges thus avoiding the activation of parasitic junctions.
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