Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

addition of signed numbers

Status
Not open for further replies.

lordsathish

Full Member level 5
Joined
Feb 11, 2006
Messages
246
Helped
33
Reputation
66
Reaction score
3
Trophy points
1,298
Location
Asia
Activity points
2,698
Hi...
I have been trying to a verilog code for 8 bit signed adder...
To add the negative number we complement it and add it with the positive number with a carry in as '1'.

However when we get the carry out of the above process as zeros then we have to compute the two's complement of the result. For this we have to complement the result and add it with 1. This will consume one more 8 bit adder.

I.E to compute the two's complement of the result if carry out is 0 takes one moe adder. Is'nt there any other better way to avoid this one more adder...
 

Using a two's complement number format, there is effectively no need for special treatment of any value, you just add binary numbers without considering a sign. Optionally, you can detect overflow from result sign: If both numbers have equal sign and the result has opposite sign, you got an overflow.
 

ya but i have to have my output to be in signed representation... so i have to find the two's complement again...
 

As an example with 4 Bit numbers

1011 + 0100 = 1111

is true for unsigned representation, where it means 11+4=15, but also for signed, meaning (-5) + 4 = -1.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top